公开(公告)号：US10101382B2

公开(公告)日：2018-10-16

申请号：US15395907

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alex Paikin ,  Colin Johnson ,  Tathagata Chatterjee ,  Sameer Pendharkar

IPC: G01R31/10 ,  G01R31/26 ,  G01R31/28

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

公开(公告)号：US20180190814A1

公开(公告)日：2018-07-05

申请号：US15394636

申请日：2016-12-29

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/22 ,  H01L21/28

CPC classification number: H01L29/7816 ,  H01L21/22 ,  H01L21/28035 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66681

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US20180190550A1

公开(公告)日：2018-07-05

申请号：US15439191

申请日：2017-02-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L21/66 ,  H01L29/06 ,  H01L23/544 ,  H01L29/40 ,  H01L29/20 ,  H01L29/417 ,  H01L27/088 ,  G01R31/12 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/12 ,  G01R31/2884 ,  H01L23/544 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/41725

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US20180102357A1

公开(公告)日：2018-04-12

申请号：US15291564

申请日：2016-10-12

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L27/0259 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/7818

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US09941383B2

公开(公告)日：2018-04-10

申请号：US15168524

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Jacek Korec ,  John Manning Savidge Neilson ,  Sameer Pendharkar

IPC: H01L29/739 ,  H01L21/331 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L29/66333 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32053 ,  H01L29/0834 ,  H01L29/7395

Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or grown epitaxial silicon for controlled drift region thickness and fast switching speed.

公开(公告)号：US20170250272A1

公开(公告)日：2017-08-31

申请号：US15597769

申请日：2017-05-17

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/778 ,  H01L21/7605 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.

公开(公告)号：US09741718B2

公开(公告)日：2017-08-22

申请号：US14803759

申请日：2015-07-20

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L21/761 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US09685545B2

公开(公告)日：2017-06-20

申请号：US14951927

申请日：2015-11-25

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/778 ,  H01L21/7605 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.

公开(公告)号：US20170133261A1

公开(公告)日：2017-05-11

申请号：US15413118

申请日：2017-01-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Eugen Mindricelu ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L21/761 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0251

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

公开(公告)号：US09559093B2

公开(公告)日：2017-01-31

申请号：US15144104

申请日：2016-05-02

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L21/338 ,  H01L27/02 ,  H01L29/20 ,  H01L29/267 ,  H01L29/778 ,  H01L49/02 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/8232 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A method of forming a semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component has a breakdown voltage less than a breakdown voltage of the GaN FET. The voltage dropping component is formed to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract translation: 形成半导体器件的方法包括具有电耦合到GaN FET的漏极节点并且与降压部件串联耦合的过电压钳位部件的GaN FET。 降压组件电耦合到为GaN FET提供截止状态偏置的端子。 过电压钳位元件的击穿电压小于GaN FET的击穿电压。 形成降压部件以提供随着过电压钳位部件的电流增加而增加的电压降。 半导体器件被配置为当跨越降压元件的电压降达到阈值时接通GaN FET。