公开(公告)号：US09806074B2

公开(公告)日：2017-10-31

申请号：US14965182

申请日：2015-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L21/225 ,  H01L21/266 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7831

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

公开(公告)号：US20170133261A1

公开(公告)日：2017-05-11

申请号：US15413118

申请日：2017-01-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Eugen Mindricelu ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L21/761 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0251

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

公开(公告)号：US20170084738A1

公开(公告)日：2017-03-23

申请号：US15364971

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L27/092 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/7835

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

公开(公告)号：US09543299B1

公开(公告)日：2017-01-10

申请号：US14861912

申请日：2015-09-22

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L27/092 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/7835

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

Abstract translation: 基于RESURF的双栅p-n双峰传导横向扩散金属氧化物半导体（LDMOS）。 在说明性实施例中，p型源电耦合到n型漏极。 p型漏极电耦合到n型源极。 n型层用作n型漏极和n型源极之间的n型导电沟道。 p型顶层设置在所述半导体器件的衬底的表面上，并且设置在n型层的上方并与其相邻。 p型顶层用作p型源极和p型漏极之间的p型导电沟道。 n栅极控制n型导电沟道中的电流，p栅极控制p型导电沟道中的电流。

公开(公告)号：US09843322B2

公开(公告)日：2017-12-12

申请号：US15067928

申请日：2016-03-11

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03L5/00 ,  H03K17/687 ,  H01L27/092 ,  H01L29/06 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7816 ,  H01L29/7831 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US09735265B2

公开(公告)日：2017-08-15

申请号：US15348725

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/762 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

公开(公告)号：US09525060B2

公开(公告)日：2016-12-20

申请号：US14563028

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

Abstract translation: 一种集成电路，包括隔离器件，隔离器件具有与深沟槽隔离相结合的较低埋层。 具有与衬底相同的导电类型的上掩埋层设置在下掩埋层上，使得在隔离器件的周边处形成与下掩埋层的电接触。 深沟槽隔离横向围绕隔离设备。 在下埋层之间的电接触足以保持对下掩埋层的期望偏压，沿着隔离器件的周边的上半部分在上掩埋层和深沟槽之间进行。

公开(公告)号：US09431480B1

公开(公告)日：2016-08-30

申请号：US14671572

申请日：2015-03-27

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Scott G. Balster

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/266 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816

Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

Abstract translation: 多指横向高压晶体管（MFLHVT）包括掺杂有第一掺杂剂类型的衬底，掺杂第二掺杂剂的衬底以及掺杂有第一类型的具有稀释BDL部分（DBDL）的掩埋漂移层（BDL），其包括稀释条纹 。 掺杂第二类型的半导体表面在BDL上。 电介质隔离区域具有限定第一间隙区域（第一MOAT）中的第一有源区域和第二间隙区域（第二MOAT）中的第二有源区域的间隙。 漏极包括第二MOAT中的漏极指与第一MOAT中的源极指与每个掺杂的第二类型相互指向。 DBDL位于指尖漂移区域内，与第一和第二MOAT之间的排水指尖和/或来源指尖相关联。 栅极堆叠在源极和漏极之间的半导体表面上。 稀释条纹具有在其各自位置处以漂移长度单调增加的条带宽度。

公开(公告)号：US09245998B2

公开(公告)日：2016-01-26

申请号：US14578710

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar

IPC: H01L29/78 ,  H01L29/76 ,  H01L21/336 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7831

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

Abstract translation: 一种具有多个电流通道的LDMOS晶体管的集成电路和方法。 第一电流通道在掩埋的p型扩散之上，并且第二个电流通道在掩埋的p型扩散之下。

公开(公告)号：US10319809B2

公开(公告)日：2019-06-11

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.