公开(公告)号：US09466590B1

公开(公告)日：2016-10-11

申请号：US14941041

申请日：2015-11-13

Applicant: International Business Machines Corporation

Inventor： Tymon Barwicz ,  Yves C. Martin ,  Jae-Woong Nah

IPC: H01L23/488 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L23/49503 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/30 ,  H01L25/167 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/0225 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06515 ,  H01L2224/09515 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11462 ,  H01L2224/13101 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: A multi-chip system includes a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the major surfaces; a bottom chip stack element comprising a bottom substrate having two major surfaces and bottom solder pads arrayed along a plane of one of the major surfaces; one or more solder reservoir pads connected to one or more of the top solder pads or of the bottom solder pads; and solder material; and wherein at least one of the top solder pads is connected to one of the bottom solder pads by one of the solder material.

Abstract translation: 多芯片系统包括顶部芯片堆叠元件，其包括具有两个主表面的顶部芯片和沿其中一个主表面的平面排列的顶部焊盘; 底部芯片堆叠元件，包括具有两个主表面的底部衬底和沿着主表面之一的平面排列的底部焊盘; 连接到一个或多个顶部焊盘或底部焊盘的一个或多个焊料储存器焊盘; 和焊料; 并且其中所述顶部焊盘中的至少一个通过所述焊料材料之一连接到所述底部焊盘之一。

公开(公告)号：US09324681B2

公开(公告)日：2016-04-26

申请号：US14497572

申请日：2014-09-26

Applicant: Tessera, Inc.

Inventor： Belgacem Haba ,  Ilyas Mohammed

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/811 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for making a microelectronic package includes the steps of providing a microelectronic assembly that further includes a substrate with a plurality of conductive elements thereon, a carrier, and a plurality of substantially rigid metal elements extending from the carrier and joined to the conductive elements; and removing the carrier from the microelectronic assembly to expose contact surfaces of the respective ones of the plurality of metal elements remote from the first conductive pads.

Abstract translation: 一种制造微电子封装的方法包括以下步骤：提供微电子组件，该微电子组件还包括其上具有多个导电元件的衬底，载体和从载体延伸并接合到导电元件的多个基本刚性的金属元件; 以及从所述微电子组件移除所述载体以暴露所述多个金属元件中相应的所述金属元件远离所述第一导电焊盘的接触表面。

公开(公告)号：US20150311177A1

公开(公告)日：2015-10-29

申请号：US14696171

申请日：2015-04-24

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyo Hoon PARK ,  Suk Min SEO ,  Jong Hun KIM ,  Sun Kyu HAN

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0213 ,  H01L2224/02135 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81009 ,  H01L2224/8102 ,  H01L2224/811 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81375 ,  H01L2224/81379 ,  H01L2224/81395 ,  H01L2224/8149 ,  H01L2224/81493 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/01014 ,  H01L2924/01006

Abstract: A chip packaging method using a hydrophobic surface includes forming superhydrophobic surfaces forming hydrophilic surfaces on predetermined positions of the superhydrophobic surfaces formed on the one of a first chip or the first board and the one of a second chip or a second board, respectively, generating liquid metal balls on the hydrophilic surfaces formed on the one of the first chip or the first board and the one of the second chip or the second board, respectively, and packaging the one of the first chip or the first board and the one of the second chip or the second board by combing the liquid metal ball of the one of the first chip or the first board and the liquid metal ball of the one of the second chip or the second board with each other.

Abstract translation: 使用疏水性表面的芯片封装方法包括在形成在第一芯片或第一板和第二芯片或第二板之一上的超疏水表面的预定位置上形成亲水表面的超疏水表面，分别产生液体 分别形成在第一芯片或第一板上的一个上的亲水表面上的金属球和第二芯片或第二板中的一个上的金属球，并且将第一芯片或第一板中的一个和第二芯片 通过将第一芯片或第一板中的一个的液态金属球和第二芯片或第二板中的一个的液态金属球彼此结合而将芯片或第二板彼此结合。

公开(公告)号：US20150123252A1

公开(公告)日：2015-05-07

申请号：US14248355

申请日：2014-04-09

Applicant: CHIPMOS TECHNOLOGIES INC.

Inventor： TSUNG JEN LIAO

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/3107 ,  H01L23/433 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/1191 ,  H01L2224/13147 ,  H01L2224/1626 ,  H01L2224/811 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2224/81904 ,  H01L2224/81951 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a package structure of a lead frame. The package includes a die, a dielectric layer, at least one conducting pillar, at least one lead frame and at least one solder ball. The dielectric layer is disposed on a surface of the die. The at least one conducting pillar penetrates through the dielectric layer and is disposed on the surface. The at least one lead frame is disposed on the dielectric layer and is spaced from the at least one conducting pillar with a gap. The solder ball fills the gap and electrically connects the at least one conducting pillar and the at least one lead frame.

Abstract translation: 本发明涉及引线框的封装结构。 封装包括裸片，电介质层，至少一个导电柱，至少一个引线框和至少一个焊球。 电介质层设置在模具的表面上。 至少一个导柱穿过介电层并设置在表面上。 所述至少一个引线框架设置在所述电介质层上并且与所述至少一个导电柱间隔开间隙。 焊球填充间隙并电连接至少一个导电柱和至少一个引线框架。

公开(公告)号：US20150011052A1

公开(公告)日：2015-01-08

申请号：US14497572

申请日：2014-09-26

Applicant: Tessera, Inc.

Inventor： Belgacem Haba ,  Ilyas Mohammed

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/811 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for making a microelectronic package includes the steps of providing a microelectronic assembly that further includes a substrate with a plurality of conductive elements thereon, a carrier, and a plurality of substantially rigid metal elements extending from the carrier and joined to the conductive elements; and removing the carrier from the microelectronic assembly to expose contact surfaces of the respective ones of the plurality of metal elements remote from the first conductive pads.

Abstract translation: 一种制造微电子封装的方法包括以下步骤：提供微电子组件，该微电子组件还包括其上具有多个导电元件的衬底，载体和从载体延伸并接合到导电元件的多个基本刚性的金属元件; 以及从所述微电子组件移除所述载体以暴露所述多个金属元件中相应的所述金属元件远离所述第一导电焊盘的接触表面。

公开(公告)号：US20140151823A1

公开(公告)日：2014-06-05

申请号：US13953238

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C.S. Chou

IPC: B81B3/00

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US20130334692A1

公开(公告)日：2013-12-19

申请号：US13527422

申请日：2012-06-19

Applicant: Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: B23K31/02 ,  H01L23/488

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Abstract translation: 一种方法包括将第一包装部件的第一电连接器与第二包装部件的第二电连接器对准。 利用第一电​​连接器与第二电连接器对准，金属层被电镀在第一和第二电连接器上。 金属层将第一电连接器连接到第二电连接器。

公开(公告)号：US08551816B2

公开(公告)日：2013-10-08

申请号：US13439198

申请日：2012-04-04

Applicant: Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

Inventor： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L21/6835 ,  H01L24/11 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06183 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16137 ,  H01L2224/16238 ,  H01L2224/17183 ,  H01L2224/81005 ,  H01L2224/811 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01054 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83851 ,  H01L2224/81

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract translation: 本发明允许使用尽可能短的信号路径进行直接芯片到芯片的连接。

公开(公告)号：US08309396B2

公开(公告)日：2012-11-13

申请号：US12616920

申请日：2009-11-12

Applicant: Kai-Ming Ching

Inventor： Kai-Ming Ching

IPC: H01L21/00 ,  H01L21/4763

CPC classification number: H01L24/05 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02126 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16059 ,  H01L2224/16147 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.

Abstract translation: 堆叠和对准多个集成电路的方法和系统。 该方法包括以下步骤：提供具有至少一个漏斗形插座的第一集成电路，提供第二集成电路，将第二集成电路上的至少一个突起与至少一个漏斗形插座对准，并将第一集成电路 集成电路到第二集成电路。 该系统包括具有至少一个漏斗形插座，设置在漏斗形插座内部的金属化扩散屏障和第二集成电路的第一集成电路。 所述至少一个漏斗形插座适于接收第二集成电路的一部分。

公开(公告)号：US20100276191A1

公开(公告)日：2010-11-04

申请号：US12839344

申请日：2010-07-19

Applicant: Hiroto Sugahara

Inventor： Hiroto Sugahara

IPC: H05K1/11

CPC classification number: H05K3/361 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/1624 ,  H01L2224/24105 ,  H01L2224/24227 ,  H01L2224/811 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H05K3/0032 ,  H05K3/363 ,  H05K2201/10477 ,  H05K2203/013 ,  H01L2924/00

Abstract: For electrically connecting a wiring formed on one surface of an insulating substrate such as an FPC to an individual electrode arranged facing the other surface of the substrate, firstly, a through hole and a notch are formed by irradiating a laser beam from above onto the FPC. Next, the FPC is arranged to be positioned such that the individual electrode, the through hole and the notch are overlapped in a plan view. Next, an electroconductive liquid droplet having a diameter greater than a width of the notch is jetted, toward an area formed with the notch, from the one surface side of the FPC. The landed electroconductive liquid droplet flows along the notch in a thickness direction of the substrate due to an action of a capillary force and reaches assuredly to the individual electrode, thereby electrically connecting the wiring and electrode arranged sandwiching the insulating substrate assuredly.

Abstract translation: 为了将形成在诸如FPC的绝缘基板的一个表面上的布线电连接到与基板的另一表面相对布置的单独电极，首先通过从上方将激光束照射到FPC上而形成通孔和凹口 。 接下来，将FPC布置成使得各个电极，通孔和凹口在平面图中重叠。 接下来，从FPC的一个表面侧向具有凹口的区域喷射直径大于凹口宽度的导电液滴。 着陆的导电液滴由于毛细管力的作用而沿着基板的厚度方向沿着切口流动，并且确实地到达各个电极，从而可靠地将布线和电极布置在绝缘基板上。