公开(公告)号：US09634007B2

公开(公告)日：2017-04-25

申请号：US14302350

申请日：2014-06-11

Applicant: Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

公开(公告)号：US20170110448A1

公开(公告)日：2017-04-20

申请号：US14884388

申请日：2015-10-15

Applicant: Infineon Technologies Austria AG

Inventor： Gerhard Prechtl ,  Bernhard Zojer

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L21/8258 ,  H01L27/0694 ,  H01L27/085 ,  H01L27/0883 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787 ,  H03K2217/0054

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

公开(公告)号：US20170093394A1

公开(公告)日：2017-03-30

申请号：US15374059

申请日：2016-12-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA

IPC: H03K17/687 ,  H01L29/786 ,  H01L27/06

CPC classification number: H03K17/687 ,  H01L21/8258 ,  H01L23/58 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/7869 ,  H01L2924/0002 ,  H03K19/0013 ,  H03K2217/0027 ,  H01L2924/00

Abstract: A semiconductor device having excellent data retention characteristics. A transistor with a low off-state current is utilized to save and retain data stored in a memory circuit, and a potential to be applied to a back gate of the transistor is applied from a battery provided for each memory circuit. The potential applied to the back gate of the transistor and a potential for charging the battery are generated in a voltage generation circuit. The battery is charged utilizing power gating of the memory circuit and data retention characteristics is improved.

公开(公告)号：US20170092547A1

公开(公告)日：2017-03-30

申请号：US15234170

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poren Tang ,  Sunjung Steve KIM ,  Moon Seung YANG ,  Seung Hun LEE ,  Hyun Jung LEE ,  Geun Hee JEONG

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/78

Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.

公开(公告)号：US09607902B2

公开(公告)日：2017-03-28

申请号：US14813435

申请日：2015-07-30

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Deyuan Xiao

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8258

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for forming a semiconductor structure includes sequentially providing a semiconductor substrate having NFET regions and NFET regions; forming an insulation layer on the semiconductor substrate; forming a sacrificial layer on the insulation layer; forming first trenches in the PFET regions, and second trenches in the NFET regions; forming a third trench on the bottom of each of the first trenches and the second trenches; forming a first buffer layer in each of the first trenches and the second trenches by filling the third trenches; forming a first semiconductor layer on each of the first buffer layers in the first trenches and the second teaches; removing the first semiconductor layers in the second trenches; forming a second buffer layer with a top surface lower than the insolation layer in each of second trenches; and forming a second semiconductor layer on each of the second buffer layers.

公开(公告)号：US09603190B2

公开(公告)日：2017-03-21

申请号：US15110042

申请日：2015-01-23

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  NANYANG TECHNOLOGICAL UNIVERSITY

Inventor： Pilsoon Choi ,  Jason Gao ,  Nadesh Ramanathan ,  Chirn-Chye Boon ,  Suhaib Fahmy ,  Li-Shiuan Peh

IPC: H04M1/00 ,  H04W88/06 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/092 ,  H01L23/66 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778

CPC classification number: H04W88/06 ,  H01L21/8258 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2223/665 ,  H01L2223/6655

Abstract: An integrated circuit (400) adapted for mobile communication is disclosed. The circuit comprises a first device layer formed of a first semiconductor material and having at least a first circuit portion (402); and a second device layer formed of a second semiconductor material different to the first semiconductor material and having at least a second circuit portion (404), wherein the first and second device layers are integrally formed, and the first circuit portion is electrically coupled to the second circuit portion to enable the mobile communication using first and second wireless communication protocols. A related mobile computing device is also disclosed.

公开(公告)号：US20170069596A1

公开(公告)日：2017-03-09

申请号：US15121759

申请日：2014-03-27

Applicant: Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

Inventor： Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L25/065 ,  H01L29/24 ,  H01L29/20 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0652 ,  G06F1/1652 ,  G09F9/301 ,  G09G3/3648 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/4985 ,  H01L25/00 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/2003 ,  H01L29/24 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了芯片上的多设备灵活系统（SOC）以及用于制造这种SOC的方法。 可以依次处理多材料堆叠，以在单个柔性SOC中形成多个集成电路（IC）装置。 通过从单个堆叠形成IC器件，可以通过单个金属化工艺为多个器件形成触点，并且可以将这些触点位于SOC的公共背面中。 堆叠层可以根据处理温度进行排序和处理，使得较早进行较高温度处理。 以这种方式，堆叠的中间层可以屏蔽一些堆叠层与处理堆叠的上层相关联的升高的处理温度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20170069548A1

公开(公告)日：2017-03-09

申请号：US15355483

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Tsun LIU

IPC: H01L21/8238 ,  H01L21/311 ,  H01L29/165 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/441 ,  H01L21/465 ,  H01L21/823814 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/26 ,  H01L29/4232 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.

Abstract translation: 提供了一种半导体器件结构及其形成方法。 半导体器件结构包括形成在衬底上的衬底和栅叠层结构。 半导体器件结构还包括形成在栅极堆叠结构的侧壁上的栅极间隔，并且栅极间隔物包括与顶部相邻的顶部和底部，并且底部部分倾斜到衬底的顶表面。 半导体器件结构还包括与栅极间隔物相邻形成的外延结构，并且外部结构形成在栅极间隔物的下方。

公开(公告)号：US20170069544A1

公开(公告)日：2017-03-09

申请号：US15353825

申请日：2016-11-17

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/45 ,  H01L29/16 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L21/823814 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/8258 ,  H01L23/53209 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/165 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, first and second metals, and a second semiconductor material. The substrate includes a first semiconductor material and has first and second substrate portions. The first metal is reacted with the first substrate portion of the substrate. The second semiconductor material is above the second substrate portion of the substrate and is different from the first semiconductor material. The second metal is reacted with the second semiconductor material.

Abstract translation: 半导体器件包括衬底，第一和第二金属和第二半导体材料。 衬底包括第一半导体材料并且具有第一和第二衬底部分。 第一金属与基板的第一基板部分反应。 第二半导体材料在基板的第二基板部分上方，并且与第一半导体材料不同。 第二金属与第二半导体材料反应。

公开(公告)号：US09590051B2

公开(公告)日：2017-03-07

申请号：US15026614

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Patrick Morrow

IPC: H01L27/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/41 ,  H01L27/092 ,  H01L29/36 ,  H01L29/417

CPC classification number: H01L29/267 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/413 ,  H01L29/4175 ,  H01L29/66439 ,  H01L29/775

Abstract: An embodiment includes an apparatus comprising: an N layer comprising an NMOS device having a N channel, source, and drain that are all intersected by a first horizontal axis that is parallel to a substrate; a P layer comprising a PMOS device having a P channel, source, and drain that are all intersected by a second horizontal axis that is parallel to the substrate; a first gate, corresponding to the N channel, which intersects the second horizontal axis; and a second gate, corresponding to the P channel, which intersects the first horizontal axis. Other embodiments are described herein.

Abstract translation: 实施例包括一种装置，包括：N层，包括具有N沟道，源极和漏极的NMOS器件，所述N沟道，源极和漏极都与平行于衬底的第一水平轴相交; P层，包括具有P沟道，源极和漏极的PMOS器件，所述PMOS器件都与平行于衬底的第二水平轴相交; 对应于与第二水平轴相交的N通道的第一门; 以及与P沟道相对应的与第一水平轴相交的第二门。 本文描述了其它实施例。