公开(公告)号：US08716751B2

公开(公告)日：2014-05-06

申请号：US13631417

申请日：2012-09-28

Applicant: Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L21/02

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract translation: 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US08026509B2

公开(公告)日：2011-09-27

申请号：US12319102

申请日：2008-12-30

Applicant: Niti Goel ,  Wilman Tsai ,  Jack Kavalieros

Inventor： Niti Goel ,  Wilman Tsai ,  Jack Kavalieros

IPC: H01L29/78

CPC classification number: H01L29/7391 ,  H01L29/205 ,  H01L29/66356

Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

Abstract translation: TFET包括源极区（110,210），漏极区（120,220），在源极区和漏极区之间的沟道区（130,230）以及与该区域相邻的栅极区域（140,240） 渠道区域。 源极区域包含包含第一III族材料和第一V族材料的第一化合物半导体，并且沟道区域包含包含第二III族材料和第二V族材料的第二化合物半导体。 漏极区域可以包含第三化合物半导体，其包括第三III族材料和第三族V族材料。

公开(公告)号：US09634007B2

公开(公告)日：2017-04-25

申请号：US14302350

申请日：2014-06-11

Applicant: Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

公开(公告)号：US08936976B2

公开(公告)日：2015-01-20

申请号：US12646711

申请日：2009-12-23

Applicant: Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

Inventor： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L21/338 ,  H01L29/778 ,  H01L21/225 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract translation: 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：US08765563B2

公开(公告)日：2014-07-01

申请号：US13630527

申请日：2012-09-28

Applicant: Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/8222 ,  H01L21/30 ,  H01L21/20 ,  H01L29/15

CPC classification number: H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

Abstract translation: 沟槽限制的选择性外延生长工艺，其中半导体器件层的外延生长在沟槽的范围内进行。 在实施例中，制造沟槽以包括设置在沟槽底部的原始平面半导体晶种表面。 接种表面周围的半导体区域可以相对于接种表面凹陷，其中隔离电介质设置在其上以包围半导体晶种层并形成沟槽。 在形成沟槽的实施例中，牺牲性硬掩模翅片可以被覆盖在电介质中，然后将其平坦化以暴露硬掩模翅片，然后将其去除以暴露接种表面。 通过选择性异质外延从种子表面形成半导体器件层。 在实施例中，通过使隔离电介质的顶表面凹陷，从半导体器件层形成非平面器件。 在实施例中，可以从半导体器件层制造具有高载流子迁移率的非平面器件CMOS器件。

公开(公告)号：US20140091360A1

公开(公告)日：2014-04-03

申请号：US13630527

申请日：2012-09-28

Applicant: Ravi PILLARISETTY ,  Seung Hoon SUNG ,  Niti GOEL ,  Jack T. KAVALIEROS ,  Sansaptak DASGUPTA ,  Van H. LE ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Robert S. CHAU

Inventor： Ravi PILLARISETTY ,  Seung Hoon SUNG ,  Niti GOEL ,  Jack T. KAVALIEROS ,  Sansaptak DASGUPTA ,  Van H. LE ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Robert S. CHAU

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/336

CPC classification number: H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

Abstract translation: 沟槽限制的选择性外延生长工艺，其中半导体器件层的外延生长在沟槽的范围内进行。 在实施例中，制造沟槽以包括设置在沟槽底部的原始平面半导体晶种表面。 接种表面周围的半导体区域可以相对于接种表面凹陷，其中隔离电介质设置在其上以包围半导体晶种层并形成沟槽。 在形成沟槽的实施例中，牺牲性硬掩模翅片可以被覆盖在电介质中，然后将其平坦化以暴露硬掩模翅片，然后将其去除以暴露接种表面。 通过选择性异质外延从种子表面形成半导体器件层。 在实施例中，通过使隔离电介质的顶表面凹陷，从半导体器件层形成非平面器件。 在实施例中，可以从半导体器件层制造具有高载流子迁移率的非平面器件CMOS器件。

公开(公告)号：US08686402B2

公开(公告)日：2014-04-01

申请号：US13224661

申请日：2011-09-02

Applicant: Niti Goel ,  William Tsai ,  Jack Kavalieros

Inventor： Niti Goel ,  William Tsai ,  Jack Kavalieros

IPC: H01L29/20 ,  H01L29/12

CPC classification number: H01L29/7391 ,  H01L29/205 ,  H01L29/66356

Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

Abstract translation: TFET包括源极区（110,210），漏极区（120,220），在源极区和漏极区之间的沟道区（130,230）以及与该区域相邻的栅极区域（140,240） 渠道区域。 源极区域包含包含第一III族材料和第一V族材料的第一化合物半导体，并且沟道区域包含包含第二III族材料和第二V族材料的第二化合物半导体。 漏极区域可以包含第三化合物半导体，其包括第三III族材料和第三族V族材料。

公开(公告)号：US20100163845A1

公开(公告)日：2010-07-01

申请号：US12319102

申请日：2008-12-30

Applicant: Niti Goel ,  Wilman Tsai ,  Jack Kavalieros

Inventor： Niti Goel ,  Wilman Tsai ,  Jack Kavalieros

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7391 ,  H01L29/205 ,  H01L29/66356

Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

Abstract translation: TFET包括源极区（110,210），漏极区（120,220），在源极区和漏极区之间的沟道区（130,230）以及与该区域相邻的栅极区域（140,240） 渠道区域。 源极区域包含包含第一III族材料和第一V族材料的第一化合物半导体，并且沟道区域包含包含第二III族材料和第二V族材料的第二化合物半导体。 漏极区域可以包含第三化合物半导体，其包括第三III族材料和第三族V族材料。

公开(公告)号：US09711591B2

公开(公告)日：2017-07-18

申请号：US13997607

申请日：2011-12-28

Applicant: Niloy Mukherjee ,  Matthew V. Metz ,  James M. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel ,  Loren Chow ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Niloy Mukherjee ,  Matthew V. Metz ,  James M. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel ,  Loren Chow ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/06

CPC classification number: H01L29/06 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/0259 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02658 ,  H01L21/02664

Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

公开(公告)号：US20170018543A1

公开(公告)日：2017-01-19

申请号：US15124817

申请日：2014-06-25

Applicant: Rany T. ELSAYED ,  Niti GOEL ,  Silvio E. BOU-GHAZALE ,  Randy J. AKSAMIT

Inventor： Rany T. ELSAYED ,  Niti GOEL ,  Silvio E. BOU-GHAZALE ,  Randy J. AKSAMIT

IPC: H01L27/02 ,  H01L21/027 ,  H01L27/118 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/16

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11807 ,  H01L29/16 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H03K19/00

Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

Abstract translation: 公开了用于使用下一代光刻（NGL）工艺（例如电子束直写（EBDW）和极紫外光刻（EUVL））形成功能电池的压实阵列的技术，以形成阵列中的电池的边界。 紧凑的单元阵列可以用于配置有逻辑单元，配置有位单元的静态随机存取存储器（SRAM）结构或具有基于单元的结构的其他存储器或逻辑器件的现场可编程门阵列（FPGA）结构。 与常规的193nm光刻相比，这些技术可以用于获得10至50％的面积减少，例如对于功能单元阵列，因为NGL工艺允许更高的精度和更小的细胞边界切割 。 此外，使用NGL工艺来形成单元的边界也可以减少光刻引起的变化，否则将以传统的193nm光刻法存在。