公开(公告)号：US08716131B2

公开(公告)日：2014-05-06

申请号：US13653176

申请日：2012-10-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Fa Chen ,  Chen-Shien Chen

IPC: H01L21/44

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2224/05552

Abstract: A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.

Abstract translation: 公开了一种用于形成凹凸金属化层的系统和方法，其通过硅通孔和迹线减少了UBM的总体占地面积。 优选实施例包括在多个通孔上形成凸起下金属化层，而UBM仅连接到其所位于的硅通孔总数的一部分。 连接到贯通硅通孔的迹线可另外形成在UBM之下，以在模具表面上节省更多的空间。

公开(公告)号：US20140103540A1

公开(公告)日：2014-04-17

申请号：US14132515

申请日：2013-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming Hung Tseng ,  Chen-Shien Chen

IPC: H01L23/46 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/46 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Abstract translation: 集成电路结构包括：具有半导体衬底的裸片; 半导体衬底上的电介质层; 包括电介质层中的金属线和通孔的互连结构; 从所述半导体衬底的内部延伸到所述电介质层的内部的多个沟道; 以及在所述多个通道的互连结构和密封部分上的电介质膜。 多个通道被配置成允许流体流过。

公开(公告)号：US20140035148A1

公开(公告)日：2014-02-06

申请号：US13733692

申请日：2013-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD

Inventor： Yao-Chun Chuang ,  Chita Chuang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/488

CPC classification number: H01L24/13 ,  H01L23/488 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2224/16104 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

Abstract translation: 上述实施例提供了封装和接合基板之间的结合结构的扩大的重叠表面积。 通过在封装和/或接合衬底上使用细长的结合结构并且通过使这种结合结构定向，结合结构被设计成承受由热循环引起的结合应力以减少冷接头。

公开(公告)号：US20240355795A1

公开(公告)日：2024-10-24

申请号：US18659033

申请日：2024-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Dong-Han Shen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/24 ,  H01L25/18 ,  H01L25/0652 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/181 ,  H01L2924/3511

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

公开(公告)号：US12125715B2

公开(公告)日：2024-10-22

申请号：US18341052

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Ching Hsu ,  Yu-Huan Chen ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/4853 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81035 ,  H01L2224/81047 ,  H01L2224/81192 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81493

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a nickel layer over the first pad. The nickel layer has a T-shape in a cross-sectional view of the nickel layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip.

公开(公告)号：US12119276B2

公开(公告)日：2024-10-15

申请号：US18360465

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wen-Yi Lin ,  Kuang-Chun Lee ,  Chien-Chen Li ,  Chen-Shien Chen

IPC: H01L23/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/053 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L23/10 ,  H01L21/4817 ,  H01L23/053 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/562 ,  H01L24/06 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/16195

Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The first adhesive element has a first electrical resistivity, and the second adhesive element has a second electrical resistivity. The second electrical resistivity is greater than the first electrical resistivity. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.

公开(公告)号：US12119237B2

公开(公告)日：2024-10-15

申请号：US18349292

申请日：2023-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Li Kuo ,  Chin-Fu Kao ,  Chen-Shien Chen

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L21/4882 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L21/56 ,  H01L24/27 ,  H01L24/743 ,  H01L24/75 ,  H01L2224/214

Abstract: A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device.

公开(公告)号：US12087718B2

公开(公告)日：2024-09-10

申请号：US18300493

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16056 ,  H01L2224/16059 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/384 ,  Y10T428/12493 ,  Y10T428/24479

Abstract: The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.

公开(公告)号：US12046588B2

公开(公告)日：2024-07-23

申请号：US17672719

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Dong-Han Shen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/24 ,  H01L25/18 ,  H01L25/0652 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/181 ,  H01L2924/3511

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

公开(公告)号：US20230369152A1

公开(公告)日：2023-11-16

申请号：US18356243

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Huan Chiu ,  Chun-Jen Chen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Kuo-Hui Chang ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/565 ,  H01L24/03 ,  H01L23/3171 ,  H01L24/09 ,  H01L2924/1811 ,  H01L2224/02379 ,  H01L25/0756

Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.