公开(公告)号：US09583451B2

公开(公告)日：2017-02-28

申请号：US14744495

申请日：2015-06-19

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11001 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01027

Abstract: Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed on the first conductive layer to define a conductive pillar. The conductive pillar includes a non-planar top surface defining a recess. The recess may receive a portion of a solder body used to connect the conductive pillar with a package.

Abstract translation: 支柱式连接和制造柱式连接的方法。 在接合焊盘上形成导电层。 在第一导电层上形成第二导电层以限定导电柱。 导电柱包括限定凹部的非平面顶表面。 凹部可以接收用于将导电柱与包装物连接的焊料体的一部分。

公开(公告)号：US09231046B2

公开(公告)日：2016-01-05

申请号：US13840132

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L23/00

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L24/11 ,  H01L24/13 ,  H01L27/0805 ,  H01L28/60 ,  H01L2224/13009 ,  H01L2224/48463 ,  H01L2924/14 ,  H01L2924/19041

Abstract: A metal-insulator-metal (MIM) capacitor using barrier layer metallurgy and methods of manufacture are disclosed. The method includes forming a bottom plate of a metal-insulator-metal (MIM) capacitor and a bonding pad using a single masking process. The method further includes forming a MIM dielectric on the bottom plate. The method further includes forming a top plate of the MIM capacitor on the MIM dielectric. The method further includes forming a solder connection on the bonding pad.

Abstract translation: 公开了一种使用阻挡层冶金和制造方法的金属绝缘体金属（MIM）电容器。 该方法包括使用单一掩蔽工艺形成金属 - 绝缘体 - 金属（MIM）电容器的底板和接合焊盘。 该方法还包括在底板上形成MIM电介质。 该方法还包括在MIM电介质上形成MIM电容器的顶板。 该方法还包括在焊盘上形成焊接连接​​。

公开(公告)号：US09165850B2

公开(公告)日：2015-10-20

申请号：US14525682

申请日：2014-10-28

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06102 ,  H01L2224/11848 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.

Abstract translation: 制造倒装芯片封装的结构和方法，其采用距离用于倒装芯片封装的集成电路（IC）芯片的中心的径向距离的不同高度的聚酰亚胺焊盘。 聚酰亚胺焊盘可以形成在电连接器下面，电连接器将IC芯片连接到倒装芯片封装的芯片载体，使得形成在更高高度的聚酰亚胺焊盘上的电连接器设置在离IC芯片中心更大的径向距离处 而形成在较低高度的聚酰亚胺焊盘上的电连接器更靠近IC芯片的中心设置。 与IC芯片表面相对高的电连接器可以补偿在制造倒装芯片封装期间由热引起的翘曲产生的间隙，其将IC芯片上的电连接器与芯片载体上的倒装芯片分离 。

公开(公告)号：US20150097283A1

公开(公告)日：2015-04-09

申请号：US14048483

申请日：2013-10-08

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/7684 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/014

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.

Abstract translation: 焊接凸块连接和制造焊料凸点连接的方法。 在电介质层上形成钝化层。 通孔从钝化层的顶表面延伸穿过钝化层到钝化层中的金属线。 导电层形成在钝化层的顶表面上并在每个通孔开口内。 当钝化层和导电层平坦化时，形成包括通孔开口中的部分的插塞。 每个部分与金属线连接。

公开(公告)号：US20140319522A1

公开(公告)日：2014-10-30

申请号：US13870026

申请日：2013-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Karen P. McLaughlin ,  Ekta Misra ,  Christopher D. Muzzy ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/11914 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).

Abstract translation: 公开了半导体晶片处理期间的金属化方法和所得到的结构。 在该方法中，钝化层被图案化，其中第一开口在上方对齐并垂直延伸到下面的金属结构。 形成掩模层并用第一开口对准的第二开口进行图案化，从而形成垂直延伸穿过掩模层和钝化层到下面的金属结构的两层开口。 电沉积工艺在双层开口中形成凸点下焊盘和附加的金属部件，其不同于凸块下焊盘（例如，引线焊盘;最终垂直的） 裂缝结构部分和/或探针垫）。 每个凸点下焊盘和附加的金属特征最初包括铜上的金属盖层。 除去掩模层，形成另外的掩模层并用仅暴露凸块下焊盘的第三开口图案化，并且将焊料材料沉积在凸块下焊盘上。

公开(公告)号：US20140187034A1

公开(公告)日：2014-07-03

申请号：US14200613

申请日：2014-03-07

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract translation: 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US08492267B1

公开(公告)日：2013-07-23

申请号：US13633449

申请日：2012-10-02

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/4763

CPC classification number: H01L21/76885 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815

Abstract: Pillar interconnect chip to package and global wiring structures and methods of manufacturing are discloses. The method includes forming a resist directly over at least one landing pad and at least one wiring layer, and forming a first pattern in the resist over the landing pad and a second pattern over the wiring layer, using a single lithography step. The method further includes forming metal in the first pattern in electrical contact with the landing pad. The method further includes removing remaining resist over the wiring layer to deepen the second pattern. The method further includes forming a pillar interconnect in the first pattern and a wiring in the second pattern by adding additional metal on the metal in the first pattern and over the at least one wiring layer in the second pattern, respectively. The method further includes removing any remaining resist.

Abstract translation: 柱式互连芯片封装和全局布线结构及制造方法均公开。 该方法包括直接在至少一个着陆焊盘和至少一个布线层上形成抗蚀剂，并且使用单个平版印刷步骤，在着色焊盘上的抗蚀剂中形成第一图案，并在布线层上形成第二图案。 该方法还包括在第一图案中形成与着陆垫电接触的金属。 该方法还包括去除布线层上的剩余抗蚀剂以加深第二图案。 该方法还包括通过在第一图案中的金属上添加额外的金属和在第二图案中的至少一个布线层上分别在第一图案中形成柱互连和第二图案中的布线。 该方法还包括去除任何剩余的抗蚀剂。

公开(公告)号：US20130140695A1

公开(公告)日：2013-06-06

申请号：US13758386

申请日：2013-02-04

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  George J. Scott

IPC: H01L23/00

CPC classification number: H01L24/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/051 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05562 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/11 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01027 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.

Abstract translation: 焊接凸块连接和制造焊料凸点连接的方法。 该方法包括形成包含第一和第二导电层的层叠层，在第二导电层的顶表面上形成电介质钝化层，以及形成延伸穿过介电钝化层的通孔至第二导电层的顶表面。 该方法还包括在通孔开口中形成导电塞。 焊料凸点连接包括由不同导体组成的第一和第二导电层，在第二导电层的顶表面上的介电钝化层，延伸穿过介电钝化层到第二导电层顶表面的通孔，以及 导电塞在通孔开口中。

公开(公告)号：US11270964B2

公开(公告)日：2022-03-08

申请号：US16030973

申请日：2018-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Christopher D. Muzzy

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/498

Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

公开(公告)号：US20200303339A1

公开(公告)日：2020-09-24

申请号：US16358658

申请日：2019-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHARLES L. ARVIN ,  Clement J. Fortin ,  Christopher D. Muzzy ,  Krishna R. Tunga ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/532

Abstract: Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.