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公开(公告)号:US20190259683A1
公开(公告)日:2019-08-22
申请号:US16404949
申请日:2019-05-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: CHARLES L. ARVIN , STEVEN P. OSTRANDER , KRISHNA R. TUNGA
IPC: H01L23/367 , F28F21/08 , H01L23/373 , H01L21/48
Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.
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公开(公告)号:US20190164864A1
公开(公告)日:2019-05-30
申请号:US15826856
申请日:2017-11-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: CHARLES L. ARVIN , STEVEN P. OSTRANDER , KRISHNA R. TUNGA
IPC: H01L23/367 , H01L23/373 , H01L21/48 , F28F21/08
Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.
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公开(公告)号:US20180331056A1
公开(公告)日:2018-11-15
申请号:US16030973
申请日:2018-07-10
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: CHARLES L. ARVIN , CHRISTOPHER D. MUZZY
IPC: H01L23/00 , H01L23/498 , H01L21/66
CPC classification number: H01L24/06 , H01L22/20 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05113 , H01L2224/05155 , H01L2224/05647 , H01L2224/05666 , H01L2224/0603 , H01L2224/06131 , H01L2224/06132 , H01L2224/06134 , H01L2224/06177 , H01L2224/11001 , H01L2224/1145 , H01L2224/11462 , H01L2224/116 , H01L2224/1161 , H01L2224/13026 , H01L2224/13028 , H01L2224/13078 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/13562 , H01L2224/136 , H01L2224/13639 , H01L2224/16227 , H01L2224/81815 , H01L2924/07025 , H01L2924/014 , H01L2924/00014 , H01L2924/00012
Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.
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公开(公告)号:US20200303339A1
公开(公告)日:2020-09-24
申请号:US16358658
申请日:2019-03-19
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: CHARLES L. ARVIN , Clement J. Fortin , Christopher D. Muzzy , Krishna R. Tunga , Thomas Weiss
IPC: H01L23/00 , H01L23/532
Abstract: Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.
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公开(公告)号:US20200161272A1
公开(公告)日:2020-05-21
申请号:US16773368
申请日:2020-01-27
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: CHARLES L. ARVIN , CLEMENT J. FORTIN , CHRISTOPHER D. MUZZY , BRIAN W. QUINLAN , THOMAS A. WASSICK , THOMAS WEISS
IPC: H01L23/00 , H01L23/498
Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.
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公开(公告)号:US20200098723A1
公开(公告)日:2020-03-26
申请号:US16695121
申请日:2019-11-25
Applicant: International Business Machines Corporation
Inventor: CHARLES L. ARVIN , Christopher D. Muzzy
IPC: H01L23/00 , H01L23/498
Abstract: A semiconductor structure which includes a first semiconductor substrate having a first plurality of copper connectors; a second semiconductor substrate having a second plurality of copper connectors; and a joining structure joining the first plurality of copper connectors to the second plurality of copper connectors, the joining structure including a copper intermetallic mesh having pores filled with silver.
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公开(公告)号:US20190006312A1
公开(公告)日:2019-01-03
申请号:US15640475
申请日:2017-07-01
Applicant: International Business Machines Corporation
Inventor: CHARLES L. ARVIN , Clement Fortin , Christopher D. Muzzy , Brian W. Quinlan , Thomas A. Wassick , Thomas Weiss
IPC: H01L23/00 , H01L23/498
Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.
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