MULTIPART LID FOR A SEMICONDUCTOR PACKAGE WITH MULTIPLE COMPONENTS

    公开(公告)号:US20190164864A1

    公开(公告)日:2019-05-30

    申请号:US15826856

    申请日:2017-11-30

    Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

    MULTIPART LID FOR A SEMICONDUCTOR PACKAGE WITH MULTIPLE COMPONENTS

    公开(公告)号:US20190259683A1

    公开(公告)日:2019-08-22

    申请号:US16404949

    申请日:2019-05-07

    Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

    OPTIMIZED INDIVIDUAL SLEEP PATTERNS
    3.
    发明申请

    公开(公告)号:US20180368756A1

    公开(公告)日:2018-12-27

    申请号:US15631064

    申请日:2017-06-23

    Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.

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