公开(公告)号：US20210320056A1

公开(公告)日：2021-10-14

申请号：US16845404

申请日：2020-04-10

Applicant: International Business Machines Corporation

Inventor： Krishna R. Tunga ,  Thomas Weiss ,  Charles Leon Arvin ,  Bhupender Singh ,  Brian W. Quinlan

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L21/50

Abstract: An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

公开(公告)号：US11121101B2

公开(公告)日：2021-09-14

申请号：US16777169

申请日：2020-01-30

Applicant: International Business Machines Corporation

Inventor： Charles Leon Arvin ,  Karen P. McLaughlin ,  Thomas Anthony Wassick ,  Brian W. Quinlan

IPC: H01L21/00 ,  H01L23/00

Abstract: Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.

公开(公告)号：US11004614B2

公开(公告)日：2021-05-11

申请号：US16211345

申请日：2018-12-06

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Sylvain Pharand ,  Bhupender Singh ,  Brian W. Quinlan

IPC: H01G4/38 ,  H01G4/228 ,  H01L23/66 ,  H01G4/248 ,  H01G4/30 ,  H01G4/35

Abstract: A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.

公开(公告)号：US10431563B1

公开(公告)日：2019-10-01

申请号：US15948038

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20190006312A1

公开(公告)日：2019-01-03

申请号：US15640475

申请日：2017-07-01

Applicant: International Business Machines Corporation

Inventor： CHARLES L. ARVIN ,  Clement Fortin ,  Christopher D. Muzzy ,  Brian W. Quinlan ,  Thomas A. Wassick ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/498

Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

公开(公告)号：US20180053717A1

公开(公告)日：2018-02-22

申请号：US15796770

申请日：2017-10-28

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jean Audet ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Brian R. Sundlof

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

公开(公告)号：US09601423B1

公开(公告)日：2017-03-21

申请号：US14974484

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jon A. Casey ,  Brian M. Erwin ,  Steven P. Ostrander ,  Brian W. Quinlan

IPC: H01L21/02 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/16 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element.

公开(公告)号：US11388821B2

公开(公告)日：2022-07-12

申请号：US16851424

申请日：2020-04-17

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Jean Audet ,  Francesco Preda

IPC: H05K1/18 ,  H01G4/33 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K3/30 ,  H05K1/16 ,  H05K1/02

Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

公开(公告)号：US11239183B2

公开(公告)日：2022-02-01

申请号：US16779529

申请日：2020-01-31

Applicant: International Business Machines Corporation

Inventor： Tuhin Sinha ,  Krishna R. Tunga ,  Brian W. Quinlan ,  Charles Leon Arvin ,  Steven Paul Ostrander ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/16 ,  H01L23/14 ,  H01L21/48 ,  H01L23/66 ,  H01L23/538

Abstract: A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

公开(公告)号：US20210057341A1

公开(公告)日：2021-02-25

申请号：US16546912

申请日：2019-08-21

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Karen P. McLaughlin ,  Brian W. Quinlan ,  Thomas Weiss

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

Abstract: A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.