公开(公告)号：US11825592B2

公开(公告)日：2023-11-21

申请号：US17062926

申请日：2020-10-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Chenzhou Lian ,  Kathryn C. Rivera ,  Paul F. Bodenweber ,  Jon A. Casey

IPC: H05K1/00 ,  H05K1/02 ,  H05K7/20

CPC classification number: H05K1/0203 ,  H05K7/20127 ,  Y10T29/49002

Abstract: An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.

公开(公告)号：US11410894B2

公开(公告)日：2022-08-09

申请号：US16562583

申请日：2019-09-06

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Richard F. Indyk ,  Bhupender Singh ,  Jon A. Casey ,  Shidong Li

IPC: H01L23/34 ,  H01L23/13 ,  H01L23/373 ,  H01L23/367 ,  G06F3/00 ,  H01L23/00 ,  H01L25/065

Abstract: An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

公开(公告)号：US20210074599A1

公开(公告)日：2021-03-11

申请号：US16562583

申请日：2019-09-06

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Richard F. Indyk ,  Bhupender Singh ,  Jon A. Casey ,  Shidong Li

IPC: H01L23/13 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  G06F3/00

Abstract: An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

公开(公告)号：US09477568B2

公开(公告)日：2016-10-25

申请号：US14039047

申请日：2013-09-27

Applicant: International Business Machines Corporation

Inventor： Malcolm S. Allen-Ware ,  Jon A. Casey ,  Sungjun Chun ,  Alan J. Drake ,  Charles R. Lefurgy ,  Karthick Rajamani ,  Jeonghee Shin ,  Thomas A. Wassick ,  Victor Zyuban

IPC: G06F17/50 ,  G06F11/30 ,  G06F11/07 ,  G06F11/00

CPC classification number: G06F11/3006 ,  G06F11/004 ,  G06F11/0703 ,  G06F11/3027 ,  G06F11/3058 ,  G06F11/3093

Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.

Abstract translation: 提供了一种用于确定一组多核处理器中的一组核心中的一组互连组的建模年龄的机制。 对于多核处理器集合中的一组核心中的一组互连组中的每个互连组，确定互连组的当前建模年龄。 然后确定用于该组互连组的互连组的至少一个当前建模年龄是否大于寿命终止值。 响应于互连组的至少一个当前建模年龄大于寿命终止值，发送与至少一个相关联的互连组采取校正动作的指示。

公开(公告)号：US20150094995A1

公开(公告)日：2015-04-02

申请号：US14039047

申请日：2013-09-27

Applicant: International Business Machines Corporation

Inventor： Malcolm S. Allen-Ware ,  Jon A. Casey ,  Sungjun Chun ,  Alan J. Drake ,  Charles R. Lefurgy ,  Karthick Rajamani ,  Jeonghee Shin ,  Thomas A. Wassick ,  Victor Zyuban

IPC: G06F11/30

CPC classification number: G06F11/3006 ,  G06F11/004 ,  G06F11/0703 ,  G06F11/3027 ,  G06F11/3058 ,  G06F11/3093

Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.

Abstract translation: 提供了一种用于确定一组多核处理器中的一组核心中的一组互连组的建模年龄的机制。 对于多核处理器集合中的一组核心中的一组互连组中的每个互连组，确定互连组的当前建模年龄。 然后确定用于该组互连组的互连组的至少一个当前建模年龄是否大于寿命终止值。 响应于互连组的至少一个当前建模年龄大于寿命终止值，发送与至少一个相关联的互连组采取校正动作的指示。

公开(公告)号：US11177217B2

公开(公告)日：2021-11-16

申请号：US16738196

申请日：2020-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Jon A. Casey ,  Joshua Rubin ,  Arvind Kumar ,  Dinesh Gupta ,  Charles L. Arvin ,  Mark W. Kapfhammer ,  Steve Ostrander ,  Maryse Cournoyer ,  Valérie A. Oberson ,  Lawrence A. Clevenger

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

公开(公告)号：US10834808B2

公开(公告)日：2020-11-10

申请号：US14867413

申请日：2015-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Paul F. Bodenweber ,  Jon A. Casey ,  Chenzhou Lian ,  Kathryn C. Rivera ,  Kamal K. Sikka

IPC: H05K1/02 ,  H05K7/20

Abstract: An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation.

公开(公告)号：US20190295952A1

公开(公告)日：2019-09-26

申请号：US15926044

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Jon A. Casey ,  Joshua Rubin ,  Arvind Kumar ,  Dinesh Gupta ,  Charles L. Arvin ,  Mark W. Kapfhammer ,  Steve Ostrander ,  Maryse Cournoyer ,  Valérie A. Oberson ,  Lawrence A. Clevenger

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

公开(公告)号：US10580738B2

公开(公告)日：2020-03-03

申请号：US15926044

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Jon A. Casey ,  Joshua Rubin ,  Arvind Kumar ,  Dinesh Gupta ,  Charles L. Arvin ,  Mark W. Kapfhammer ,  Steve Ostrander ,  Maryse Cournoyer ,  Valérie A. Oberson ,  Lawrence A. Clevenger

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

公开(公告)号：US09601423B1

公开(公告)日：2017-03-21

申请号：US14974484

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jon A. Casey ,  Brian M. Erwin ,  Steven P. Ostrander ,  Brian W. Quinlan

IPC: H01L21/02 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/16 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element.