公开(公告)号：US10784202B2

公开(公告)日：2020-09-22

申请号：US15828463

申请日：2017-12-01

Applicant: International Business Machines Corporation

Inventor： Francois Arguin ,  Luc Guerin ,  Maryse Cournoyer ,  Steve E. Whitehead ,  Jean Audet ,  Richard D. Langlois ,  Christian Bergeron ,  Pascale Gagnon ,  Nathalie Meunier

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.

公开(公告)号：US11791270B2

公开(公告)日：2023-10-17

申请号：US17315859

申请日：2021-05-10

Applicant: International Business Machines Corporation

Inventor： Kamal K Sikka ,  Maryse Cournoyer ,  Pascale Gagnon ,  Charles C. Bureau ,  Catherine Dufort ,  Dale Curtis McHerron ,  Vijayeshwar Das Khanna ,  Marc A. Bergendahl ,  Dishit Paresh Parekh ,  Ravi K. Bonam ,  Hiroyuki Mori ,  Yang Liu ,  Paul S. Andry ,  Isabel De Sousa

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4867 ,  H01L23/13 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/16257 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/1616 ,  H01L2924/1632 ,  H01L2924/3512

Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

公开(公告)号：US20210233892A1

公开(公告)日：2021-07-29

申请号：US16752642

申请日：2020-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Paul S. Andry ,  Yang Liu ,  Pascale Gagnon ,  Christian Bergeron ,  Maryse Cournoyer

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/42 ,  H01L23/31 ,  H01L25/00

Abstract: An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.

公开(公告)号：US20200279840A1

公开(公告)日：2020-09-03

申请号：US16288946

申请日：2019-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BARNIM ALEXANDER JANTA-POLCZYNSKI ,  Isabel De Sousa ,  Jean Audet ,  Maryse Cournoyer ,  Sylvain Pharand ,  Roxan Lemire ,  Louis-Marie Achard ,  Paul Francis Fortier

IPC: H01L25/18 ,  G02B6/26 ,  H01L23/13 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48

Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.

公开(公告)号：US10580738B2

公开(公告)日：2020-03-03

申请号：US15926044

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Jon A. Casey ,  Joshua Rubin ,  Arvind Kumar ,  Dinesh Gupta ,  Charles L. Arvin ,  Mark W. Kapfhammer ,  Steve Ostrander ,  Maryse Cournoyer ,  Valérie A. Oberson ,  Lawrence A. Clevenger

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

公开(公告)号：US20220359401A1

公开(公告)日：2022-11-10

申请号：US17315859

申请日：2021-05-10

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Maryse Cournoyer ,  Pascale Gagnon ,  Charles C. Bureau ,  Catherine Dufort ,  Dale Curtis McHerron ,  Vijayeshwar Das Khanna ,  Marc A. Bergendahl ,  Dishit Paresh Parekh ,  RAVI K. BONAM ,  HIROYUKI MORI ,  Yang Liu ,  Paul S. Andry ,  Isabel De Sousa

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/13 ,  H01L21/48

Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

公开(公告)号：US11209598B2

公开(公告)日：2021-12-28

申请号：US16288946

申请日：2019-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Barnim Alexander Janta-Polczynski ,  Isabel De Sousa ,  Jean Audet ,  Maryse Cournoyer ,  Sylvain Pharand ,  Roxan Lemire ,  Louis-Marie Achard ,  Paul Francis Fortier

IPC: G02B6/30

Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.

公开(公告)号：US10991635B2

公开(公告)日：2021-04-27

申请号：US16517568

申请日：2019-07-20

Applicant: International Business Machines Corporation

Inventor： Dale Curtis McHerron ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Ravi K. Bonam ,  Ramachandra Divakaruni ,  William J. Starke ,  Maryse Cournoyer

IPC: H01L23/538 ,  H01L23/13 ,  H01L27/24 ,  H01L23/532

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

公开(公告)号：US11177217B2

公开(公告)日：2021-11-16

申请号：US16738196

申请日：2020-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Jon A. Casey ,  Joshua Rubin ,  Arvind Kumar ,  Dinesh Gupta ,  Charles L. Arvin ,  Mark W. Kapfhammer ,  Steve Ostrander ,  Maryse Cournoyer ,  Valérie A. Oberson ,  Lawrence A. Clevenger

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

公开(公告)号：US11139269B2

公开(公告)日：2021-10-05

申请号：US16752642

申请日：2020-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Paul S. Andry ,  Yang Liu ,  Pascale Gagnon ,  Christian Bergeron ,  Maryse Cournoyer

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/42 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

Abstract: An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.