公开(公告)号：US11209598B2

公开(公告)日：2021-12-28

申请号：US16288946

申请日：2019-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Barnim Alexander Janta-Polczynski ,  Isabel De Sousa ,  Jean Audet ,  Maryse Cournoyer ,  Sylvain Pharand ,  Roxan Lemire ,  Louis-Marie Achard ,  Paul Francis Fortier

IPC: G02B6/30

Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.

公开(公告)号：US20200104454A1

公开(公告)日：2020-04-02

申请号：US16149313

申请日：2018-10-02

Applicant: International Business Machines Corporation

Inventor： Jean Audet ,  Alain Ayotte ,  Franklin Baez ,  Anson Call ,  Deana Cosmadelis ,  Jason Lee Frankel ,  Kevin Grosselfinger ,  Roxan Lemire ,  Marek Andrzej Orlowski ,  Gilles Poitras ,  Paul Robert Walling

IPC: G06F17/50

Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.

公开(公告)号：US10423751B2

公开(公告)日：2019-09-24

申请号：US15719698

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Jean Audet ,  Franklin M. Baez ,  Jason L. Frankel ,  Paul R. Walling

IPC: G06F17/50

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

公开(公告)号：US09673064B2

公开(公告)日：2017-06-06

申请号：US14874393

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： Jean Audet ,  Benjamin V. Fasano ,  Shidong Li

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/15 ,  H01L21/027 ,  H01L25/065

CPC classification number: H01L21/486 ,  H01L21/0274 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.

公开(公告)号：US11388821B2

公开(公告)日：2022-07-12

申请号：US16851424

申请日：2020-04-17

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Jean Audet ,  Francesco Preda

IPC: H05K1/18 ,  H01G4/33 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K3/30 ,  H05K1/16 ,  H05K1/02

Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

公开(公告)号：US10813215B2

公开(公告)日：2020-10-20

申请号：US15068891

申请日：2016-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jean Audet ,  Edmund D. Blackshear ,  Masahiro Fukui ,  Charles L. Reynolds ,  Kenji Terada ,  Tomoyuki Yamada

IPC: H05K1/03 ,  H01L23/498 ,  H01L23/00 ,  H01L51/44 ,  H01L51/10 ,  H01L51/52 ,  H01L23/14

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

公开(公告)号：US10687420B2

公开(公告)日：2020-06-16

申请号：US15068884

申请日：2016-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jean Audet ,  Edmund D. Blackshear ,  Masahiro Fukui ,  Charles L. Reynolds ,  Kenji Terada ,  Tomoyuki Yamada

IPC: H05K1/03 ,  H01L23/498 ,  H01L23/00 ,  H01L51/44 ,  H01L51/10 ,  H01L51/52 ,  H01L23/14

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

公开(公告)号：US20190172787A1

公开(公告)日：2019-06-06

申请号：US15828463

申请日：2017-12-01

Applicant: International Business Machines Corporation

Inventor： Francois Arguin ,  Luc Guerin ,  Maryse Cournoyer ,  Steve E. Whitehead ,  Jean Audet ,  Richard D. Langlois ,  Christian Bergeron ,  Pascale Gagnon ,  Nathalie Meunier

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.

公开(公告)号：US10949600B2

公开(公告)日：2021-03-16

申请号：US16539120

申请日：2019-08-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jean Audet ,  Franklin M. Baez ,  Jason L. Frankel ,  Paul R. Walling

IPC: G06F30/398 ,  G06F30/392 ,  G06F113/18

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

公开(公告)号：US20200279840A1

公开(公告)日：2020-09-03

申请号：US16288946

申请日：2019-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BARNIM ALEXANDER JANTA-POLCZYNSKI ,  Isabel De Sousa ,  Jean Audet ,  Maryse Cournoyer ,  Sylvain Pharand ,  Roxan Lemire ,  Louis-Marie Achard ,  Paul Francis Fortier

IPC: H01L25/18 ,  G02B6/26 ,  H01L23/13 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48

Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.