公开(公告)号：US10546096B2

公开(公告)日：2020-01-28

申请号：US15719693

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Paul R. Walling

IPC: G06F17/50

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.

公开(公告)号：US10375820B2

公开(公告)日：2019-08-06

申请号：US15928090

申请日：2018-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

IPC: H05K1/02 ,  H05K1/11 ,  G06F17/50

Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

公开(公告)号：US10956649B2

公开(公告)日：2021-03-23

申请号：US16547623

申请日：2019-08-22

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Francesco Preda ,  Paul R. Walling

IPC: G06F30/398 ,  G06F30/394 ,  G06F111/10 ,  G06F113/18 ,  G06F113/20

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

公开(公告)号：US10423751B2

公开(公告)日：2019-09-24

申请号：US15719698

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Jean Audet ,  Franklin M. Baez ,  Jason L. Frankel ,  Paul R. Walling

IPC: G06F17/50

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

公开(公告)号：US20190102506A1

公开(公告)日：2019-04-04

申请号：US15719743

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Francesco Preda ,  Paul R. Walling

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/16 ,  G06F2217/38 ,  G06F2217/40

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

公开(公告)号：US09955567B2

公开(公告)日：2018-04-24

申请号：US14341834

申请日：2014-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

IPC: H05K1/02 ,  G06F17/50 ,  H05K1/11

CPC classification number: H05K1/0224 ,  G06F17/5081 ,  H05K1/116 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/09727 ,  Y10T29/49004 ,  Y10T29/49155 ,  Y10T29/53022

Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

公开(公告)号：US10949600B2

公开(公告)日：2021-03-16

申请号：US16539120

申请日：2019-08-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jean Audet ,  Franklin M. Baez ,  Jason L. Frankel ,  Paul R. Walling

IPC: G06F30/398 ,  G06F30/392 ,  G06F113/18

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

公开(公告)号：US10423752B2

公开(公告)日：2019-09-24

申请号：US15719743

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Francesco Preda ,  Paul R. Walling

IPC: G06F17/50

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

公开(公告)号：US20190102505A1

公开(公告)日：2019-04-04

申请号：US15719698

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Jean Audet ,  Franklin M. Baez ,  Jason L. Frankel ,  Paul R. Walling

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/40

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

公开(公告)号：US20190102504A1

公开(公告)日：2019-04-04

申请号：US15719693

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Paul R. Walling

IPC: G06F17/50

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.