公开(公告)号：US20150001714A1

公开(公告)日：2015-01-01

申请号：US14485207

申请日：2014-09-12

申请人： International Business Machines Corporation ,  DISCO Corporation

发明人： Richard F. Indyk ,  Ian D. Melville ,  Shigefumi Okada

IPC分类号： H01L23/00

CPC分类号： H01L24/09 ,  H01L21/561 ,  H01L21/78 ,  H01L21/782 ,  H01L23/492 ,  H01L23/562 ,  H01L24/17 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/0901 ,  H01L2224/0905 ,  H01L2224/16225 ,  H01L2224/17104 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/11

摘要： A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

摘要翻译： 衬底包括以栅格图案排列并且通过沟道区彼此横向间隔开的多个半导体芯片。 衬底包括半导体层的垂直堆叠和嵌入金属互连结构的至少一个电介质材料层。 所述至少一个介电材料层沿着沟道区域和栅格图案的顶点被去除，使得每个半导体芯片包括不平行于栅格图案的角的角面。 角面可以包括直的表面或凸面。 半导体芯片被切割并随后结合到使用底部填充材料的封装衬底上。 拐角表面减少在接合过程和随后的热循环过程中施加到金属互连层的机械应力。

公开(公告)号：US11410894B2

公开(公告)日：2022-08-09

申请号：US16562583

申请日：2019-09-06

申请人： International Business Machines Corporation

发明人： Charles L. Arvin ,  Richard F. Indyk ,  Bhupender Singh ,  Jon A. Casey ,  Shidong Li

IPC分类号： H01L23/34 ,  H01L23/13 ,  H01L23/373 ,  H01L23/367 ,  G06F3/00 ,  H01L23/00 ,  H01L25/065

摘要： An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

公开(公告)号：US20210074599A1

公开(公告)日：2021-03-11

申请号：US16562583

申请日：2019-09-06

申请人： International Business Machines Corporation

发明人： Charles L. Arvin ,  Richard F. Indyk ,  Bhupender Singh ,  Jon A. Casey ,  Shidong Li

IPC分类号： H01L23/13 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  G06F3/00

摘要： An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

公开(公告)号：US10211175B2

公开(公告)日：2019-02-19

申请号：US13689805

申请日：2012-11-30

申请人： International Business Machines Corporation ,  DISCO Corporation

发明人： Richard F. Indyk ,  Ian D. Melville ,  Shigefumi Okada

IPC分类号： H01L23/00 ,  H01L21/782 ,  H01L23/492 ,  H01L21/78 ,  H01L21/56

摘要： A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

公开(公告)号：US10134577B2

公开(公告)日：2018-11-20

申请号：US14718747

申请日：2015-05-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Richard F. Indyk ,  Deepika Priyadarshini ,  Spyridon Skordas ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Kevin R. Winstel

IPC分类号： H01L21/02 ,  B32B3/02 ,  B32B3/30 ,  B32B7/12

摘要： Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.

公开(公告)号：US20140151879A1

公开(公告)日：2014-06-05

申请号：US13689805

申请日：2012-11-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DISCO CORPORATION

发明人： Richard F. Indyk ,  Ian D. Melville ,  Shigefumi Okada

IPC分类号： H01L21/782 ,  H01L23/492

CPC分类号： H01L24/09 ,  H01L21/561 ,  H01L21/78 ,  H01L21/782 ,  H01L23/492 ,  H01L23/562 ,  H01L24/17 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/0901 ,  H01L2224/0905 ,  H01L2224/16225 ,  H01L2224/17104 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/11

摘要： A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

摘要翻译： 衬底包括以栅格图案排列并且通过沟道区彼此横向间隔开的多个半导体芯片。 衬底包括半导体层的垂直堆叠和嵌入金属互连结构的至少一个电介质材料层。 所述至少一个介电材料层沿着沟道区域和栅格图案的顶点被去除，使得每个半导体芯片包括不平行于栅格图案的角的角面。 角面可以包括直的表面或凸面。 半导体芯片被切割并随后结合到使用底部填充材料的封装衬底上。 拐角表面减少在接合过程和随后的热循环过程中施加到金属互连层的机械应力。