知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.041 秒)

    Stress-resilient chip structure and dicing process
    2.
    发明授权
    Stress-resilient chip structure and dicing process 有权

    公开(公告)号：US10211175B2

    公开(公告)日：2019-02-19

    申请号：US13689805

    申请日：2012-11-30

    申请人： International Business Machines Corporation ,  DISCO Corporation

    发明人： Richard F. Indyk ,  Ian D. Melville ,  Shigefumi Okada

    IPC分类号： H01L23/00 ,  H01L21/782 ,  H01L23/492 ,  H01L21/78 ,  H01L21/56

    摘要： A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

    SEMICONDUCTOR WAFER WITH NONSTICK SEAL REGION
    4.
    发明申请
    SEMICONDUCTOR WAFER WITH NONSTICK SEAL REGION 审中-公开
    具有非粘性密封区域的半导体滤波器

    公开(公告)号：US20150303102A1

    公开(公告)日：2015-10-22

    申请号：US14258421

    申请日：2014-04-22

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Charles L. Arvin ,  Nitin Jadhav ,  Ian D. Melville ,  Freddie Torres ,  Michael D. Webster

    IPC分类号： H01L21/768 ,  H01L21/027

    CPC分类号： H01L21/76885 ,  C25D5/022 ,  C25D7/123 ,  C25D17/004 ,  H01L21/2885

    摘要： A semiconductor wafer includes a nonstick region. During integrated circuit fabrication processes, the wafer may be inserted into an electrodeposition (e.g. plating, etc.) tool. The tool may contact the nonstick region to e.g. prevent leaks, prevent plating upon a shorting layer of the wafer, etc. When the wafer is removed the nonstick region has a propensity to not transfer to the tool, improving tool availability and reducing wafer scraps. The nonstick region may contain a nonstick seal formed from a liquid photoresist based material, an organic dielectric, etc.

    摘要翻译： 半导体晶片包括不粘区域。 在集成电路制造工艺期间，晶片可以插入到电沉积（例如电镀等）工具中。 该工具可以接触不粘区域。 防止泄漏，防止电镀在晶片的短路层等上。当去除晶片时，不粘区域具有不转移到工具的倾向，提高工具可用性并减少晶片废料。 不粘区域可以包含由液态光致抗蚀剂基材料，有机电介质等形成的不粘密封。