公开(公告)号：US20140239508A1

公开(公告)日：2014-08-28

申请号：US14185872

申请日：2014-02-20

申请人： Shinko Electric Industries Co., LTD.

发明人： Sumihiro Ichikawa ,  Takaharu Yamano

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/03464 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/9205 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate. A through hole extends through the semiconductor substrate. A first insulating layer covers an upper surface of the semiconductor substrate and includes an opening in communication with the through hole. An insulating film covers wall surfaces of the through hole and the opening. A through electrode is formed in the through hole and the opening. A first connection terminal includes an electroless plating metal layer formed on an end surface of the through electrode and an end surface of the insulating film. The first connection terminal has a larger diameter than the through electrode. A wiring pattern is laminated on a lower surface of the semiconductor substrate. An electrode pad is connected to the wiring pattern. The through electrode is connected to the wiring pattern.

摘要翻译： 半导体器件包括半导体衬底。 通孔延伸穿过半导体衬底。 第一绝缘层覆盖半导体衬底的上表面并且包括与通孔连通的开口。 绝缘膜覆盖通孔和开口的壁表面。 在通孔和开口中形成通孔。 第一连接端子包括形成在通孔的端面上的无电电镀金属层和绝缘膜的端面。 第一连接端子具有比通孔更大的直径。 在半导体基板的下表面层叠有布线图案。 电极焊盘连接到布线图案。 通孔电极连接到布线图案。

公开(公告)号：US20140217580A1

公开(公告)日：2014-08-07

申请号：US14170809

申请日：2014-02-03

申请人： Samsung Electronics Co., Ltd.

发明人： Jong Yun MYUNG ,  Yonghwan KWON

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11906 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2924/15311 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device includes a bonding pad on a semiconductor substrate, a bump on the bonding pad, a solder on the bump, and an anti-wetting layer between the bump and the solder extending along a sidewall of the bump, the anti-wetting layer having a first thickness T1 along the sidewall of the bump closer to the solder and a second thickness T2 along the sidewall of the bump closer to the bonding pad, wherein T2

摘要翻译： 一种半导体器件包括：半导体衬底上的焊盘，焊盘上的凸块，凸块上的焊料，以及沿着凸块的侧壁延伸的凸块和焊料之间的防潮湿层，防湿层 沿凸块的靠近焊料的侧壁具有第一厚度T1，沿凸点的侧壁更靠近焊盘的第二厚度T2，其中T2

公开(公告)号：US08766439B2

公开(公告)日：2014-07-01

申请号：US12634741

申请日：2009-12-10

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/12

CPC分类号： H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

摘要： Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

摘要翻译： 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US08736083B2

公开(公告)日：2014-05-27

申请号：US12431766

申请日：2009-04-29

申请人： Sheng-Shu Yang ,  Hsiao-Ting Lee ,  Chao-Chyun An

发明人： Sheng-Shu Yang ,  Hsiao-Ting Lee ,  Chao-Chyun An

IPC分类号： H01L23/544

CPC分类号： H01L24/16 ,  H01L22/12 ,  H01L22/30 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13027 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/14515 ,  H01L2224/16105 ,  H01L2224/81345 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15788 ,  H05K1/0269 ,  H05K3/323 ,  H05K2201/0133 ,  H05K2201/0367 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

摘要： A bonding inspection structure is provided. The bonding inspection structure includes at least a elastic bump located on a substrate. At least an opening is formed in the top portion of the elastic bump. An inspection area of the top portion of the elastic bump is larger than an area of the opening.

摘要翻译： 提供接合检查结构。 接合检查结构至少包括位于基板上的弹性凸块。 至少在弹性凸块的顶部形成开口。 弹性凸块的顶部的检查区域大于开口的面积。

公开(公告)号：US20140124922A1

公开(公告)日：2014-05-08

申请号：US13846570

申请日：2013-03-18

申请人： SK HYNIX INC.

发明人： Taek Joong KIM ,  Yong Su HAN

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/053

摘要： The bump structure includes a metal pattern disposed on an electrode pad to have a vertical sidewall and a recessed region surrounded by the vertical sidewalls, a metal post including a lower portion inserted into the recessed region and a protruded portion upwardly extending from the lower portion, and a passivation spacer on a sidewall of the metal post. The metal post is electrically connected to the electrode pad.

摘要翻译： 凸起结构包括设置在电极焊盘上的金属图案，具有垂直侧壁和由垂直侧壁包围的凹陷区域，金属柱包括插入凹入区域中的下部部分和从下部向上延伸的突出部分， 以及在金属柱的侧壁上的钝化间隔物。 金属柱电连接到电极焊盘。

公开(公告)号：US20140051244A1

公开(公告)日：2014-02-20

申请号：US14064358

申请日：2013-10-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Cheng KUO ,  Chen-Shien CHEN

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of forming an integrated circuit device includes forming an under-bump metallurgy (UBM) layer overlying a semiconductor substrate. Next, a first photoresist film is formed on the UBM layer where the first photoresist film has a first photosensitivity and a first thickness. Additionally, the method includes forming a second photoresist film on the first photoresist film. Next, the method includes performing an exposure process on the second photoresist film and the first photoresist film. The method further includes removing an exposed portion of the second photoresist film to form a first opening. The method further also includes removing an exposed portion of the first photoresist film to expose a portion of the UBM layer. Furthermore, the method includes forming a copper layer in the first opening. The method also includes removing the second photoresist film and the first photoresist film where the copper layer forms a copper post.

摘要翻译： 形成集成电路器件的方法包括形成覆盖在半导体衬底上的凸点下金属（UBM）层。 接下来，在UBM层上形成第一光致抗蚀剂膜，其中第一光致抗蚀剂膜具有第一光敏性和第一厚度。 另外，该方法包括在第一光致抗蚀剂膜上形成第二光致抗蚀剂膜。 接下来，该方法包括对第二光致抗蚀剂膜和第一光致抗蚀剂膜进行曝光处理。 该方法还包括去除第二光致抗蚀剂膜的暴露部分以形成第一开口。 该方法还包括去除第一光致抗蚀剂膜的暴露部分以暴露UBM层的一部分。 此外，该方法包括在第一开口中形成铜层。 该方法还包括去除第二光致抗蚀剂膜和铜层形成铜柱的第一光致抗蚀剂膜。

公开(公告)号：US08653671B2

公开(公告)日：2014-02-18

申请号：US12940848

申请日：2010-11-05

申请人： John Hongguang Zhang

发明人： John Hongguang Zhang

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/481 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13193 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/48137 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to the chip stack. Additionally, improved heat management is provided such that the chip stack adjusts in response to thermal energy generated within the chip stack to remove heat from between chips of the stack, thereby allowing the chips to operate as desired without compromising the performance of the chip stack.

摘要翻译： 本公开提供了一种用于减轻应力并在多芯片封装的3D芯片堆叠中提供改进的热管理的系统和方法。 提供了一种应力消除装置，以使得芯片堆栈响应于压力而调节，从而减轻施加到芯片堆叠的应力。 此外，提供了改进的热管理，使得芯片堆栈响应于在芯片堆栈内产生的热能来调节以从堆叠的芯片之间移除热量，从而允许芯片根据需要进行操作而不损害芯片堆栈的性能。

公开(公告)号：US20130334692A1

公开(公告)日：2013-12-19

申请号：US13527422

申请日：2012-06-19

申请人： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

发明人： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC分类号： B23K31/02 ,  H01L23/488

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

摘要： A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

摘要翻译： 一种方法包括将第一包装部件的第一电连接器与第二包装部件的第二电连接器对准。 利用第一电​​连接器与第二电连接器对准，金属层被电镀在第一和第二电连接器上。 金属层将第一电连接器连接到第二电连接器。

公开(公告)号：US20130256871A1

公开(公告)日：2013-10-03

申请号：US13434327

申请日：2012-03-29

申请人： Roden R. Topacio ,  Neil McLellan

发明人： Roden R. Topacio ,  Neil McLellan

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump and to reduce pad parasitic capacitance are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first insulating layer over plural conductor pads of a semiconductor chip and forming an opening over each of the conductor pads. An individual solder structure is coupled to the insulating layer. The solder structure has a projection in each of the openings and in electrical contact with one of the plural conductor pads.

摘要翻译： 公开了抑制半导体芯片焊料凸块中的裂纹和分层并减少垫寄生电容的方法和装置。 一方面，提供一种制造方法，其包括在半导体芯片的多个导体焊盘上形成第一绝缘层，并且在每个导体焊盘上形成开口。 单独的焊料结构耦合到绝缘层。 焊料结构在每个开口中具有突起并且与多个导体焊盘之一电接触。

公开(公告)号：US20130241071A1

公开(公告)日：2013-09-19

申请号：US13422981

申请日：2012-03-16

申请人： Ming-Che Hsieh

发明人： Ming-Che Hsieh

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/03474 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05686 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13011 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13186 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/13299 ,  H01L2224/16112 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/05432 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

摘要： A semiconductor device has a semiconductor die. The semiconductor die has a contact pad. A first conductive layer is formed over the contact pad. A conductive shell having a hollow core is formed over the first conductive layer. A compliant material is deposited in the hollow core. The semiconductor die is mounted over a substrate with the conductive shell electrically connected to a conductive trace on the substrate. A second conductive layer is formed over the conductive shell. The compliant material is an insulating material. A bump material is deposited around the conductive shell. A pre-solder material is deposited over the conductive trace. The conductive shell has a cross-sectional width less than 7 micrometers. The second conductive layer is a conductive lip. Mounting the semiconductor die over the substrate further includes mounting the semiconductor die over the substrate in a bump on lead (BOL) configuration.

摘要翻译： 半导体器件具有半导体管芯。 半导体管芯具有接触焊盘。 在接触垫上形成第一导电层。 具有中空芯的导电壳形成在第一导电层的上方。 柔性材料沉积在中空芯中。 半导体管芯安装在衬底上，导电壳电连接到衬底上的导电迹线。 在导电外壳上形成第二导电层。 柔顺材料是绝缘材料。 凸起材料沉积在导电外壳周围。 预焊材料沉积在导电迹线上。 导电壳的横截面宽度小于7微米。 第二导电层是导电唇缘。 将半导体管芯安装在衬底上还包括将半导体管芯安装在衬底上的引线（BOL）构造上的凸块中。