-
公开(公告)号：US09035468B2
公开(公告)日：2015-05-19
申请号：US13954046
申请日：2013-07-30
发明人： Chao-Wen Shih , Yung-Ping Chiang , Chen-Chih Hsieh , Hao-Yi Tsai
CPC分类号： H01L24/11 , H01L21/56 , H01L21/78 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/92 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/0235 , H01L2224/02351 , H01L2224/0236 , H01L2224/0239 , H01L2224/03831 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05548 , H01L2224/05647 , H01L2224/1182 , H01L2224/11831 , H01L2224/13007 , H01L2224/13022 , H01L2224/13111 , H01L2224/13147 , H01L2224/1369 , H01L2224/16225 , H01L2224/16237 , H01L2224/9212 , H01L2924/013 , H01L2924/01082 , H01L2924/01047 , H01L2924/00014 , H01L2224/11 , H01L2924/01029
摘要： In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.
摘要翻译： 在形成封装结构的方法中，在半导体衬底上形成金属焊盘，在半导体衬底上形成第一高分子绝缘层。 形成穿过第一聚合物绝缘层的开口以暴露金属垫的一部分。 在第一聚合物绝缘层的开口内和第一聚合物绝缘层上沉积含铜材料，从而在第一聚合物绝缘层上形成具有第一厚度和第一宽度的含铜层。 在含铜层上形成具有第二宽度的导电凸块，其中第二宽度小于第一宽度。 使用导电凸块作为掩模蚀刻含铜层的暴露部分，直到暴露部分被还原成第二厚度，从而形成整体含铜结构。
-
公开(公告)号：US20150130020A1
公开(公告)日：2015-05-14
申请号：US14077528
申请日：2013-11-12
发明人： CHAO-WEN SHIH , KAI-CHIANG WU , CHING-FENG YANG , MING-KAI LIU , SHIH-WEI LIANG , YEN-PING WANG
IPC分类号： H01L23/00 , H01L49/02 , H01L23/528
CPC分类号： H01L24/11 , H01L21/56 , H01L21/565 , H01L23/291 , H01L23/3114 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02175 , H01L2224/03828 , H01L2224/0401 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/10145 , H01L2224/1134 , H01L2224/11849 , H01L2224/13007 , H01L2224/13023 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/81191 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2924/181 , H01L2924/00 , H01L2924/014 , H01L2924/01047
摘要： The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
摘要翻译： 本公开提供一种半导体封装，其包括衬底，钝化层，具有顶表面的钝化后互连（PPI）; 和导电结构。 PPI的顶表面包括接收导电结构的第一区域和围绕第一区域的第二区域。 第二区域包括由第一区域制成的材料转化的金属衍生物。 本公开提供一种制造半导体封装的方法，包括形成覆盖PPI顶表面的一部分的第一焊剂层; 将由第一通量层未覆盖的PPI的顶表面的一部分转换为金属衍生物层; 去除第一通量层; 在PPI的第一区域上形成第二通量层; 将焊球放在焊剂层上; 并在焊球和PPI之间形成电连接。
-
公开(公告)号：US09029259B2
公开(公告)日：2015-05-12
申请号：US13716759
申请日：2012-12-17
CPC分类号： H01L31/02005 , H01L23/13 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L27/14634 , H01L27/1469 , H01L31/18 , H01L2224/10145 , H01L2224/11005 , H01L2224/1145 , H01L2224/1146 , H01L2224/11474 , H01L2224/1148 , H01L2224/13007 , H01L2224/13017 , H01L2224/13021 , H01L2224/13023 , H01L2224/13109 , H01L2224/13144 , H01L2224/16145 , H01L2224/81141 , H01L2224/81143 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/81898 , H01L2225/06513 , H01L2225/06593 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012
摘要： A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.
摘要翻译： 自对准杂交法，能够实现具有自对准和失去保护的小像素间距杂交。 该方法需要提供第一IC，其表面包括用于连接到配合IC的至少一个电触点，在IC的表面上沉积绝缘层，图案化和蚀刻绝缘层，以在绝缘层中的每一个之上提供凹部 电触点，以及在每个凹部中沉积可变形的导电材料。 提供了配合IC，其包括定位成与第一芯片上的相应凹部中的可变形导电材料对准的导电针。 然后通过使导电针与凹部中的可变形导电材料接触来使第一和配合IC杂化，使得导电材料变形并且引脚与第一IC的电触头电接触。
-
54.发明授权公开(公告)号：US09006902B2
公开(公告)日：2015-04-14
申请号：US14161034
申请日：2014-01-22
发明人： Ju-Il Choi , Su-Kyoung Kim , Kun-Sang Park , Seong-Min Son , Jin-Ho An , Do-Sun Lee
IPC分类号： H01L23/48 , H01L21/4763 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76898 , H01L23/481 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L25/0657 , H01L2224/02351 , H01L2224/03462 , H01L2224/0384 , H01L2224/0401 , H01L2224/05547 , H01L2224/05548 , H01L2224/05556 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/06181 , H01L2224/13 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13024 , H01L2224/13025 , H01L2224/13027 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer. A through electrode is provided in the through hole. A spacer is provided between the semiconductor substrate and the through electrode. An interconnection in continuity with the through electrode is provided on the insulating layer. A barrier layer covering a side and a bottom of the interconnection and a side of the through electrode is provided and the barrier layer is formed in one body.
摘要翻译： 提供了半导体器件，其在半导体衬底上具有绝缘层。 绝缘层和半导体衬底限定穿透半导体衬底和绝缘层的通孔。 通孔中设置有贯通电极。 在半导体衬底和贯通电极之间设置间隔物。 在绝缘层上设置与通孔电连接的互连。 设置覆盖互连的一侧和底部的阻挡层和通孔的一侧，并且阻挡层形成在一体中。
-
公开(公告)号：US20150035139A1
公开(公告)日：2015-02-05
申请号：US13954046
申请日：2013-07-30
发明人： Chao-Wen Shih , Yung-Ping Chiang , Chen-Chih Hsieh , Hao-Yi Tsai
IPC分类号： H01L23/00
CPC分类号： H01L24/11 , H01L21/56 , H01L21/78 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/92 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/0235 , H01L2224/02351 , H01L2224/0236 , H01L2224/0239 , H01L2224/03831 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05548 , H01L2224/05647 , H01L2224/1182 , H01L2224/11831 , H01L2224/13007 , H01L2224/13022 , H01L2224/13111 , H01L2224/13147 , H01L2224/1369 , H01L2224/16225 , H01L2224/16237 , H01L2224/9212 , H01L2924/013 , H01L2924/01082 , H01L2924/01047 , H01L2924/00014 , H01L2224/11 , H01L2924/01029
摘要： In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.
摘要翻译： 在形成封装结构的方法中，在半导体衬底上形成金属焊盘，在半导体衬底上形成第一高分子绝缘层。 形成穿过第一聚合物绝缘层的开口以暴露金属垫的一部分。 在第一聚合物绝缘层的开口内和第一聚合物绝缘层上沉积含铜材料，从而在第一聚合物绝缘层上形成具有第一厚度和第一宽度的含铜层。 在含铜层上形成具有第二宽度的导电凸块，其中第二宽度小于第一宽度。 使用导电凸块作为掩模蚀刻含铜层的暴露部分，直到暴露部分被还原成第二厚度，从而形成整体含铜结构。
-
公开(公告)号：US20140363927A1
公开(公告)日：2014-12-11
申请号：US13912652
申请日：2013-06-07
发明人： Dror Hurwitz , Alex Huang
CPC分类号： H05K1/0298 , H01L23/49822 , H01L24/13 , H01L24/81 , H01L2224/13007 , H01L2224/13022 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16235 , H01L2224/16237 , H01L2224/16238 , H01L2224/81191 , H01L2224/81193 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2924/12042 , H01L2924/15788 , H05K1/115 , H05K3/0082 , H05K3/108 , H05K3/282 , H05K3/4007 , H05K2201/0347 , H05K2201/0367 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H05K2203/1476 , H01L2924/00 , H01L2924/00014 , H01L2924/014
摘要： A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.
摘要翻译： 一种将芯片附着到具有外层的方法，外层包括嵌入电介质如焊料掩模中的通孔，通孔的端部与所述电介质齐平，所述方法包括以下步骤：（o）任选地除去有机清漆 ，（p）将具有用焊料凸块端接的腿的芯片定位成与通孔柱的暴露端接触，和（q）施加热量以熔化焊料凸块并用焊料润湿通孔的端部。
-
57.发明申请METHOD OF MAKING A CONDUCTIVE PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE 有权制造具有非金属防护结构的导电支柱的方法公开(公告)号：US20140335687A1
公开(公告)日：2014-11-13
申请号：US14444759
申请日：2014-07-28
发明人： Yi-Wen WU , Cheng-Chung LIN , Chien Ling HWANG , Chung-Shi LIU
IPC分类号： H01L21/768
CPC分类号： H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0345 , H01L2224/0401 , H01L2224/05023 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05541 , H01L2224/05568 , H01L2224/05582 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/05687 , H01L2224/10145 , H01L2224/11002 , H01L2224/1112 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11827 , H01L2224/11831 , H01L2224/11849 , H01L2224/11912 , H01L2224/13005 , H01L2224/13007 , H01L2224/13023 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/1312 , H01L2224/13123 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/1317 , H01L2224/13171 , H01L2224/13181 , H01L2224/13551 , H01L2224/13561 , H01L2224/13565 , H01L2224/1357 , H01L2224/1358 , H01L2224/13582 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13686 , H01L2224/13687 , H01L2224/13688 , H01L2224/1369 , H01L2224/81192 , H01L2224/81193 , H01L2224/814 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/05442 , H01L2924/0665 , H01L2924/07025 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/3841 , H01L2924/0105 , H01L2224/11 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/00 , H01L2224/05552
摘要： A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.
摘要翻译： 制造半导体器件的方法包括在衬底上形成凸块下金属（UBM）层，UBM层包括侧壁和表面区域。 所述方法还包括在所述UBM层上形成导电柱，所述导电柱包括侧壁，其中所述导电柱暴露所述UBM层的表面区域。 所述方法还包括在所述导电柱的侧壁上形成非金属保护结构，其中所述非金属保护结构接触所述UBM层的表面区域，并且所述非金属保护结构暴露所述UBM层的侧壁。
-
公开(公告)号：US08847388B2
公开(公告)日：2014-09-30
申请号：US13267200
申请日：2011-10-06
申请人： Chen-Hua Yu , Hung-Pin Chang , An-Jhih Su , Tsang-Jiuh Wu , Wen-Chih Chiou , Shin-Puu Jeng
发明人： Chen-Hua Yu , Hung-Pin Chang , An-Jhih Su , Tsang-Jiuh Wu , Wen-Chih Chiou , Shin-Puu Jeng
CPC分类号： H01L23/293 , H01L23/3192 , H01L24/01 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05571 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10126 , H01L2224/11334 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13006 , H01L2224/13007 , H01L2224/13018 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/15788 , H01L2924/014 , H01L2924/00012 , H01L2924/04941 , H01L2924/01047 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof.
摘要翻译： 半导体器件包括形成在钝化后互连（PPI）线上并由保护结构包围的凸块结构。 保护结构包括聚合物层和至少一个电介质层。 电介质层可以形成在聚合物层的顶表面上，该聚合物层的下面，插入凸起结构和聚合物层之间，插入在PPI线和聚合物层之间，覆盖聚合物层的外侧壁，或 其组合。
-
59.发明申请NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE 有权用于包装集成电路产品的新型支柱结构和制造这种支柱结构的方法公开(公告)号：US20140264890A1
公开(公告)日：2014-09-18
申请号：US13834058
申请日：2013-03-15
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L23/488 , H01L23/00
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/13 , H01L2224/0401 , H01L2224/05005 , H01L2224/05022 , H01L2224/05124 , H01L2224/05572 , H01L2224/1146 , H01L2224/11474 , H01L2224/11849 , H01L2224/11906 , H01L2224/13005 , H01L2224/13007 , H01L2224/13014 , H01L2224/13017 , H01L2224/13022 , H01L2224/1308 , H01L2224/13084 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2924/12042 , H01L2924/351 , H01L2924/3512 , H01L2924/00014 , H01L2924/01047 , H01L2924/207 , H01L2924/00
摘要： One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base.
摘要翻译： 本文公开的一个说明性支柱包括导电耦合到集成电路的接合焊盘和包括导体耦合到接合焊盘的基座的支柱，其中基部具有第一横向尺寸，并且导电耦合到基座 ，其中所述上部具有小于所述第一横向尺寸的第二横向尺寸。 本文公开的形成柱的方法包括形成基底，使得其与集成电路产品上的接合焊盘导电耦合，并且在形成基底之后，形成上部，使得其与基底导电耦合。
-
公开(公告)号：US08803318B2
公开(公告)日：2014-08-12
申请号：US13852296
申请日：2013-03-28
IPC分类号： H01L23/48
CPC分类号： H01L23/562 , H01L21/563 , H01L23/3178 , H01L24/13 , H01L2224/0401 , H01L2224/05567 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/131 , H01L2224/73204 , H01L2224/81815 , H01L2224/83365 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/14 , H01L2924/3512 , H01L2924/014 , H01L2224/13099 , H01L2224/05552
摘要： An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.
摘要翻译： 在无源区域中包括有源区域的无源区域和切割线的集成电路包括钝化层，其在氧化物层上包括外部氮化物层。 该集成电路还包括钝化层下方和被动区域中的裂纹停止点以及有源区域中的焊球。 钝化层在其中形成的沟槽位于比切割线更远离有源区域并且比切割线更靠近有源区的位置，沟槽完全穿过外部氮化物层，并且至少部分地 通过氧化层。
-
-
-
-
-
-
-
-
-
搜索结果
742 条记录 (耗时 0.02 秒)
