公开(公告)号：US09006902B2

公开(公告)日：2015-04-14

申请号：US14161034

申请日：2014-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Su-Kyoung Kim ,  Kun-Sang Park ,  Seong-Min Son ,  Jin-Ho An ,  Do-Sun Lee

IPC: H01L23/48 ,  H01L21/4763 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/02351 ,  H01L2224/03462 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer. A through electrode is provided in the through hole. A spacer is provided between the semiconductor substrate and the through electrode. An interconnection in continuity with the through electrode is provided on the insulating layer. A barrier layer covering a side and a bottom of the interconnection and a side of the through electrode is provided and the barrier layer is formed in one body.

Abstract translation: 提供了半导体器件，其在半导体衬底上具有绝缘层。 绝缘层和半导体衬底限定穿透半导体衬底和绝缘层的通孔。 通孔中设置有贯通电极。 在半导体衬底和贯通电极之间设置间隔物。 在绝缘层上设置与通孔电连接的互连。 设置覆盖互连的一侧和底部的阻挡层和通孔的一侧，并且阻挡层形成在一体中。

公开(公告)号：US11094612B2

公开(公告)日：2021-08-17

申请号：US15936019

申请日：2018-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

公开(公告)号：US10580726B2

公开(公告)日：2020-03-03

申请号：US16106645

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Ho Chun ,  Seong-Min Son ,  Hyung-Jun Jeon ,  Kwang-Jin Moon ,  Jin-Ho An ,  Ho-Jin Lee ,  Atsushi Fujisaki

IPC: H01L23/498 ,  H01L23/525 ,  H01L23/532 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.

公开(公告)号：US09865581B2

公开(公告)日：2018-01-09

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L23/532 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

公开(公告)号：US12014972B2

公开(公告)日：2024-06-18

申请号：US17403154

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/14 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/10 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/013 ,  H01L2924/01047 ,  H01L2224/03618 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

公开(公告)号：US11469202B2

公开(公告)日：2022-10-11

申请号：US17029639

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Min Son ,  Jeong-Gi Jin ,  Jin-Ho An ,  Jin-Ho Chun ,  Kwang-Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.

公开(公告)号：US20170033032A1

公开(公告)日：2017-02-02

申请号：US15163995

申请日：2016-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Hyung-Jun Jeon ,  Jum-Yong Park ,  Byung-Lyul Park ,  Ji-Soon Park ,  Jin-Ho An ,  Jin-Ho Chun

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/532 ,  H01L21/768 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76852 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3192 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2223/5446 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06151 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

Abstract translation: 半导体器件包括具有管芯区域和围绕管芯区域的划线区域的衬底，穿过管芯区域中的衬底的多个通孔结构，一部分通孔结构暴露在衬底的表面上，以及 保护层图案结构，其设置在所述基板的表面上，所述表面包围所述通孔结构的所述暴露部分的侧壁，并且具有覆盖所述划线区域的与所述通孔结构相邻的至少一部分的突出部分。

公开(公告)号：US10833032B2

公开(公告)日：2020-11-10

申请号：US16052383

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Min Son ,  Jeong-Gi Jin ,  Jin-Ho An ,  Jin-Ho Chun ,  Kwang-Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

公开(公告)号：US09691685B2

公开(公告)日：2017-06-27

申请号：US15163995

申请日：2016-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Hyung-Jun Jeon ,  Jum-Yong Park ,  Byung-Lyul Park ,  Ji-Soon Park ,  Jin-Ho An ,  Jin-Ho Chun

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/76852 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3192 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2223/5446 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06151 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

公开(公告)号：US20160163590A1

公开(公告)日：2016-06-09

申请号：US14956869

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokyoung Jung ,  Seong-Min Son ,  Jin-Ho An ,  Byung-Lyul Park ,  Ji-Soon Park ,  Ho-Jin Lee

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L24/03 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/114 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599

Abstract: Disclosed is a method of manufacturing a semiconductor device. A preliminary wafer-carrier assembly is formed in such a way that a wafer structure having a plurality of via structures is adhered to a light-penetrating carrier by a photodegradable adhesive. A wafer-carrier assembly having an optical shielding layer for inhibiting or preventing a light penetration is formed such that the wafer structure, the carrier and the adhesive are covered with the optical shielding layer except for the backside of the wafer structure through which the via structures are exposed. An interconnector is formed on the backside of the wafer structure such that the via structures make contact with the interconnector, and the wafer structure and the carrier are separated from each other by irradiating a light to the wafer-carrier assembly. Accordingly, the adhesive is inhibited or prevented from being dissolved during a plasma process on the wafer-carrier assembly.

Abstract translation: 公开了半导体器件的制造方法。 初步的晶片载体组件形成为具有多个通路结构的晶片结构通过可光降解的粘合剂粘附到透光载体上。 形成具有用于抑制或防止光穿透的光学屏蔽层的晶片载体组件，使得晶片结构，载体和粘合剂被除了晶片结构的背面之外的光学屏蔽层覆盖，通过该晶片结构， 被暴露。 在晶片结构的背面形成互连器，使得通孔结构与互连器接触，并且通过向晶片载体组件照射光而使晶片结构和载体彼此分离。 因此，在晶片载体组件的等离子体处理中，粘合剂被抑制或防止溶解。