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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240379639A1

    公开(公告)日：2024-11-14

    申请号：US18397837

    申请日：2023-12-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myung Joo Park ,  Hyung Jun Jeon ,  Pil-Kyu Kang

    IPC: H01L25/16 ,  H01L23/498 ,  H10B80/00

    Abstract: An example semiconductor package includes a structure, a first semiconductor chip disposed on an upper surface of the structure and electrically connected to the structure, a dummy semiconductor chip disposed on and contacting the upper surface of the structure, a molding layer surrounding a sidewall of the first semiconductor chip and a sidewall of the dummy semiconductor chip on the upper surface of the structure, a redistribution layer disposed on an upper surface of the first semiconductor chip, an upper surface of the dummy semiconductor chip, and an upper surface of the molding layer, a first through-via extending through the molding layer in a vertical direction and electrically connecting the structure and the redistribution layer, a second through-via extending through the dummy semiconductor chip in the vertical direction and electrically connecting the structure and the redistribution layer, and a capacitor disposed inside the dummy semiconductor chip.

    SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME 有权
    具有电极的半导体器件及其制造方法

    公开(公告)号：US20150155233A1

    公开(公告)日：2015-06-04

    申请号：US14490964

    申请日：2014-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyu-Hee Han ,  Pil-Kyu Kang ,  Taejin Yim ,  Naein Lee

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.

    Abstract translation: 本发明构思提供半导体器件及其制造方法。 该方法包括在基板上形成包括多个电介质层的金属间介电层，形成垂直贯穿金属间介电层和基板的通孔，向至少一个表面提供碳，例如包括 通过通孔露出的多个电介质层中的碳，形成覆盖通路孔的内表面的通孔电介质层，以及形成由通路孔中的通孔电介质层包围的贯通电极。

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