公开(公告)号：US20190043809A1

公开(公告)日：2019-02-07

申请号：US15909390

申请日：2018-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhee KANG ,  Jiyoung Kim ,  Taejin Yim ,  Jongmin Baek ,  Sanghoon Ahn ,  Hyeoksang Oh ,  Kyu-Hee Han

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5329

Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.

公开(公告)号：US20160148837A1

公开(公告)日：2016-05-26

申请号：US14847130

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Yim ,  Thomas Oszinda ,  Byunghee Kim ,  Sanghoon Ahn ,  Naein Lee ,  Keeyoung Jun

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843

Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Abstract translation: 一种处理多孔电介质层的方法包括制备其上形成有开口的多孔介电层和由该开口暴露的孔的基板，将第一前体供应到基板上以形成密封暴露孔的第一副密封层， 以及将第二前体供应到所述第一子密封层上以形成覆盖所述第一子密封层的第二副密封层。 第一和第二前体中的每一个包括硅，并且第二前体的分子量小于第一前体的分子量。

公开(公告)号：US09312171B2

公开(公告)日：2016-04-12

申请号：US14490964

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hee Han ,  Pil-Kyu Kang ,  Taejin Yim ,  Naein Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 该方法包括在基板上形成包括多个电介质层的金属间介电层，形成垂直贯穿金属间介电层和基板的通孔，向至少一个表面提供碳，例如包括 通过通孔露出的多个电介质层中的碳，形成覆盖通路孔的内表面的通孔电介质层，以及形成由通路孔中的通孔电介质层包围的贯通电极。

公开(公告)号：US09576848B2

公开(公告)日：2017-02-21

申请号：US14847130

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Yim ,  Thomas Oszinda ,  Byunghee Kim ,  Sanghoon Ahn ,  Naein Lee ,  Keeyoung Jun

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843

Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Abstract translation: 一种处理多孔电介质层的方法包括制备其上形成有开口的多孔介电层和由该开口暴露的孔的基板，将第一前体供应到基板上以形成密封暴露孔的第一副密封层， 以及将第二前体供应到所述第一子密封层上以形成覆盖所述第一子密封层的第二副密封层。 第一和第二前体中的每一个包括硅，并且第二前体的分子量小于第一前体的分子量。

公开(公告)号：US20150155233A1

公开(公告)日：2015-06-04

申请号：US14490964

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hee Han ,  Pil-Kyu Kang ,  Taejin Yim ,  Naein Lee

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 该方法包括在基板上形成包括多个电介质层的金属间介电层，形成垂直贯穿金属间介电层和基板的通孔，向至少一个表面提供碳，例如包括 通过通孔露出的多个电介质层中的碳，形成覆盖通路孔的内表面的通孔电介质层，以及形成由通路孔中的通孔电介质层包围的贯通电极。

公开(公告)号：US10446495B2

公开(公告)日：2019-10-15

申请号：US15909390

申请日：2018-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhee Kang ,  Jiyoung Kim ,  Taejin Yim ,  Jongmin Baek ,  Sanghoon Ahn ,  Hyeoksang Oh ,  Kyu-Hee Han

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02

Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.

公开(公告)号：US10199325B2

公开(公告)日：2019-02-05

申请号：US15792911

申请日：2017-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin Yim ,  Jongmin Baek ,  Deokyoung Jung ,  Kyuhee Han ,  Byunghee Kim ,  Jiyoung Kim ,  Naein Lee ,  Sangshin Jang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.