公开(公告)号：US20170178949A1

公开(公告)日：2017-06-22

申请号：US15374053

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Thomas Oszinda ,  Jongmin Baek ,  Sanghoon Ahn ,  Byunghee Kim ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.

公开(公告)号：US10199325B2

公开(公告)日：2019-02-05

申请号：US15792911

申请日：2017-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin Yim ,  Jongmin Baek ,  Deokyoung Jung ,  Kyuhee Han ,  Byunghee Kim ,  Jiyoung Kim ,  Naein Lee ,  Sangshin Jang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

公开(公告)号：US10186485B2

公开(公告)日：2019-01-22

申请号：US15897465

申请日：2018-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Wookyung You ,  Inoue Naoya ,  Hak-Sun Lee ,  Byung-Kwon Cho ,  Songyi Han ,  Jongmin Baek ,  Jiwon Kang ,  Byunghee Kim ,  Young-Ju Park ,  Sanghoon Ahn ,  Jiwon Yun ,  Naein Lee ,  YoungWoo Cho

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

公开(公告)号：US20180174977A1

公开(公告)日：2018-06-21

申请号：US15897465

申请日：2018-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Wookyung You ,  Inoue Naoya ,  Hak-Sun Lee ,  Byung-Kwon Cho ,  Songyi Han ,  Jongmin Baek ,  Jiwon Kang ,  Byunghee Kim ,  Young-Ju Park ,  Sanghoon Ahn ,  Jiwon Yun ,  Naein Lee ,  YoungWoo Cho

IPC: H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

公开(公告)号：US20170170184A1

公开(公告)日：2017-06-15

申请号：US15357299

申请日：2016-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Wookyung You ,  Inoue Naoya ,  Hak-Sun Lee ,  Byung-Kwon Cho ,  Songyi Han ,  Jongmin Baek ,  Jiwon Kang ,  Byunghee Kim ,  Young-Ju Park ,  Sanghoon Ahn ,  Jiwon Yun ,  Naein Lee ,  YoungWoo Cho

IPC: H01L27/105 ,  H01L29/06

CPC classification number: H01L23/53295 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

公开(公告)号：US10090381B2

公开(公告)日：2018-10-02

申请号：US15628675

申请日：2017-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Vietha Nguyen ,  Wookyung You ,  Sangshin Jang ,  Byunghee Kim ,  Kyu-Hee Han

IPC: H01L21/70 ,  H01L21/76 ,  H01L29/06

Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.

公开(公告)号：US09929099B2

公开(公告)日：2018-03-27

申请号：US15357299

申请日：2016-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Wookyung You ,  Inoue Naoya ,  Hak-Sun Lee ,  Byung-Kwon Cho ,  Songyi Han ,  Jongmin Baek ,  Jiwon Kang ,  Byunghee Kim ,  Young-Ju Park ,  Sanghoon Ahn ,  Jiwon Yun ,  Naein Lee ,  YoungWoo Cho

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

公开(公告)号：US09576848B2

公开(公告)日：2017-02-21

申请号：US14847130

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Yim ,  Thomas Oszinda ,  Byunghee Kim ,  Sanghoon Ahn ,  Naein Lee ,  Keeyoung Jun

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843

Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Abstract translation: 一种处理多孔电介质层的方法包括制备其上形成有开口的多孔介电层和由该开口暴露的孔的基板，将第一前体供应到基板上以形成密封暴露孔的第一副密封层， 以及将第二前体供应到所述第一子密封层上以形成覆盖所述第一子密封层的第二副密封层。 第一和第二前体中的每一个包括硅，并且第二前体的分子量小于第一前体的分子量。

公开(公告)号：US09972528B2

公开(公告)日：2018-05-15

申请号：US15374053

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Thomas Oszinda ,  Jongmin Baek ,  Sanghoon Ahn ,  Byunghee Kim ,  Wookyung You ,  Naein Lee

IPC: H01L29/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.

公开(公告)号：US20160148837A1

公开(公告)日：2016-05-26

申请号：US14847130

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Yim ,  Thomas Oszinda ,  Byunghee Kim ,  Sanghoon Ahn ,  Naein Lee ,  Keeyoung Jun

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843

Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Abstract translation: 一种处理多孔电介质层的方法包括制备其上形成有开口的多孔介电层和由该开口暴露的孔的基板，将第一前体供应到基板上以形成密封暴露孔的第一副密封层， 以及将第二前体供应到所述第一子密封层上以形成覆盖所述第一子密封层的第二副密封层。 第一和第二前体中的每一个包括硅，并且第二前体的分子量小于第一前体的分子量。