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    Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same
    1.
    发明授权
    Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same 有权

    公开(公告)号：US11232986B2

    公开(公告)日：2022-01-25

    申请号：US16785732

    申请日：2020-02-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Yong Bae ,  Hoon Seok Seo ,  Ki Hyun Park ,  Hak-Sun Lee

    IPC: H01L21/768

    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

    INTEGRATED CIRCUIT DEVICES INCLUDING ENLARGED VIA AND FULLY ALIGNED METAL WIRE AND METHODS OF FORMING THE SAME
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING ENLARGED VIA AND FULLY ALIGNED METAL WIRE AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20220108920A1

    公开(公告)日：2022-04-07

    申请号：US17551357

    申请日：2021-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Yong Bae ,  Hoon Seok Seo ,  Ki Hyun Park ,  Hak-Sun Lee

    IPC: H01L21/768

    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

    METHOD FOR FORMING A FINE PATTERN
    3.
    发明申请
    METHOD FOR FORMING A FINE PATTERN 审中-公开

    公开(公告)号：US20190267246A1

    公开(公告)日：2019-08-29

    申请号：US16263759

    申请日：2019-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KeunHee BAI ,  Jongchul Park ,  Seungjun Kim ,  Seungju Park ,  Young-Ju Park ,  Hak-Sun Lee

    IPC: H01L21/3065 ,  H01L21/3213 ,  H01L21/308

    Abstract: A method for forming a fine pattern includes forming line patterns and a connection pattern on a semiconductor substrate, the line patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and the connection pattern connecting portions of the line patterns adjacent to each other in the second direction, and performing an ion beam etching process on the connection pattern. The ion beam etching process provides an ion beam in an incident direction parallel to a plane defined by the first direction and a third direction perpendicular to a top surface of the semiconductor substrate, and the incident direction of the ion beam is not perpendicular to the top surface of the semiconductor substrate.

    Semiconductor device and method of fabricating the same
    5.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09190404B2

    公开(公告)日：2015-11-17

    申请号：US13949289

    申请日：2013-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hak-Sun Lee ,  Myeongcheol Kim ,  Cheol Kim ,  Sanghyun Lee

    IPC: H01L21/70 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L27/02 ,  H01L27/11 ,  H01L23/485

    CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/78 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include a transistor on a substrate comprising a gate insulating pattern, a gate electrode and an impurity region, a shared contact plug electrically connected to the gate electrode and the impurity region, and an etch-stop layer between side surfaces of the gate electrode and the shared contact. The shared contact plug may include a first conductive pattern electrically connected to the first impurity region and a second conductive pattern electrically connected to the gate electrode, and a top surface of the first conductive pattern may be higher than a top surface of the gate electrode.

    Abstract translation: 提供半导体器件及其制造方法。 器件可以包括在包括栅极绝缘图案，栅极电极和杂质区域的衬底上的晶体管，电连接到栅极电极和杂质区域的共用接触插塞以及栅极侧表面之间的蚀刻停止层 电极和共用触点。 共享接触插头可以包括电连接到第一杂质区域的第一导电图案和电连接到栅电极的第二导电图案，并且第一导电图案的顶表面可以高于栅电极的顶表面。

    Method for forming a fine pattern
    6.
    发明授权
    Method for forming a fine pattern 有权

    公开(公告)号：US10600653B2

    公开(公告)日：2020-03-24

    申请号：US16263759

    申请日：2019-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KeunHee Bai ,  Jongchul Park ,  Seungjun Kim ,  Seungju Park ,  Young-Ju Park ,  Hak-Sun Lee

    IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/3213

    Abstract: A method for forming a fine pattern includes forming line patterns and a connection pattern on a semiconductor substrate, the line patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and the connection pattern connecting portions of the line patterns adjacent to each other in the second direction, and performing an ion beam etching process on the connection pattern. The ion beam etching process provides an ion beam in an incident direction parallel to a plane defined by the first direction and a third direction perpendicular to a top surface of the semiconductor substrate, and the incident direction of the ion beam is not perpendicular to the top surface of the semiconductor substrate.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20140035048A1

    公开(公告)日：2014-02-06

    申请号：US13949289

    申请日：2013-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hak-Sun Lee ,  Myeongcheol Kim ,  Cheol Kim ,  Sanghyun Lee

    IPC: H01L27/088 ,  H01L29/78

    CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/78 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include a transistor on a substrate comprising a gate insulating pattern, a gate electrode and an impurity region, a shared contact plug electrically connected to the gate electrode and the impurity region, and an etch-stop layer between side surfaces of the gate electrode and the shared contact. The shared contact plug may include a first conductive pattern electrically connected to the first impurity region and a second conductive pattern electrically connected to the gate electrode, and a top surface of the first conductive pattern may be higher than a top surface of the gate electrode.

    Abstract translation: 提供半导体器件及其制造方法。 器件可以包括在包括栅极绝缘图案，栅极电极和杂质区域的衬底上的晶体管，电连接到栅极电极和杂质区域的共用接触插塞以及栅极侧表面之间的蚀刻停止层 电极和共用触点。 共享接触插头可以包括电连接到第一杂质区域的第一导电图案和电连接到栅电极的第二导电图案，并且第一导电图案的顶表面可以高于栅电极的顶表面。

    Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same
    8.
    发明授权
    Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same 有权

    公开(公告)号：US11876017B2

    公开(公告)日：2024-01-16

    申请号：US17551357

    申请日：2021-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Yong Bae ,  Hoon Seok Seo ,  Ki Hyun Park ,  Hak-Sun Lee

    IPC: H01L21/768

    CPC classification number: H01L21/76895 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76885

    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

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