公开(公告)号：US10109665B2

公开(公告)日：2018-10-23

申请号：US15630063

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Kwangjin Moon ,  Seokho Kim ,  Sukchul Bang ,  Jin Ho An ,  Naein Lee

IPC: H01L27/146

Abstract: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.

公开(公告)号：US09842803B2

公开(公告)日：2017-12-12

申请号：US15375567

申请日：2016-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

公开(公告)号：US20170178949A1

公开(公告)日：2017-06-22

申请号：US15374053

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Thomas Oszinda ,  Jongmin Baek ,  Sanghoon Ahn ,  Byunghee Kim ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.

公开(公告)号：US20160111538A1

公开(公告)日：2016-04-21

申请号：US14969702

申请日：2015-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract translation: 根据本发明构思的实施例，栅极形成在衬底上，并且第一间隔物，第二间隔物和第三间隔物依次形成在栅电极的侧壁上。 蚀刻衬底以形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护隔离件。 当形成凹陷区域时，去除第二间隔物的下部以在第一和第三间隔物之间​​形成间隙区域。 保护性间隔物填充间隙区域。

公开(公告)号：US09252235B2

公开(公告)日：2016-02-02

申请号：US13957912

申请日：2013-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L21/76 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract translation: 根据本发明构思的实施例，栅极形成在衬底上，并且第一间隔物，第二间隔物和第三间隔物依次形成在栅电极的侧壁上。 蚀刻衬底以形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护隔离件。 当形成凹陷区域时，去除第二间隔物的下部，以在第一和第三间隔物之间​​形成间隙区域。 保护性间隔物填充间隙区域。

公开(公告)号：US20150140747A1

公开(公告)日：2015-05-21

申请号：US14565922

申请日：2014-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Hoi Sung Chung ,  Naein Lee

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L21/823437 ,  H01L21/02636 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.

Abstract translation: 半导体器件包括设置在半导体衬底上的栅极图案，设置在形成在栅极图案侧的半导体衬底中的凹陷区域中的体外延图案，设置在整体外延图案上的插入外延图案和封盖外延 图案设置在插入物外延图案上。 本体外延图案具有为{111}晶面的上倾斜面，并且插入物外延图案包括促进插入物外延图案在上倾斜表面上的生长速率的特定元件。

公开(公告)号：US20140084350A1

公开(公告)日：2014-03-27

申请号：US14021469

申请日：2013-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Hoi Sung Chung ,  Naein Lee

IPC: H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/02636 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.

Abstract translation: 半导体器件包括设置在半导体衬底上的栅极图案，设置在形成在栅极图案侧的半导体衬底中的凹陷区域中的体外延图案，设置在整体外延图案上的插入外延图案和封盖外延 图案设置在插入物外延图案上。 本体外延图案具有为{111}晶面的上倾斜面，并且插入物外延图案包括促进插入物外延图案在上倾斜表面上的生长速率的特定元件。

公开(公告)号：US10141258B2

公开(公告)日：2018-11-27

申请号：US15659125

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Naein Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/764

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

公开(公告)号：US10049997B2

公开(公告)日：2018-08-14

申请号：US15440621

申请日：2017-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Hyoju Kim ,  Kwangjin Moon ,  Sujeong Park ,  Jubin Seo ,  Naein Lee ,  Ho-Jin Lee

IPC: H01L23/00

Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

公开(公告)号：US09929099B2

公开(公告)日：2018-03-27

申请号：US15357299

申请日：2016-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Wookyung You ,  Inoue Naoya ,  Hak-Sun Lee ,  Byung-Kwon Cho ,  Songyi Han ,  Jongmin Baek ,  Jiwon Kang ,  Byunghee Kim ,  Young-Ju Park ,  Sanghoon Ahn ,  Jiwon Yun ,  Naein Lee ,  YoungWoo Cho

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.