公开(公告)号：US11037991B2

公开(公告)日：2021-06-15

申请号：US16392099

申请日：2019-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoongoo Kang ,  Changwoo Seo ,  Dain Lee ,  Wook-Yeol Yi ,  Hoi Sung Chung

IPC: H01L45/02 ,  H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.

公开(公告)号：US09640658B2

公开(公告)日：2017-05-02

申请号：US14925679

申请日：2015-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Myungsun Kim ,  Hoi Sung Chung

IPC: H01L29/78 ,  H01L29/45 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66636

Abstract: A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

公开(公告)号：US20190386008A1

公开(公告)日：2019-12-19

申请号：US16270865

申请日：2019-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi Sung Chung ,  Tae Sung Kang ,  Dong Suk Shin ,  Kong Soo Lee ,  Jun-Won Lee

IPC: H01L27/108 ,  H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L21/311 ,  H01L21/324 ,  H01L29/08 ,  H01L29/40 ,  H01L21/266

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.

公开(公告)号：US09299836B2

公开(公告)日：2016-03-29

申请号：US14626211

申请日：2015-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Hoi Sung Chung ,  Dongsuk Shin ,  Naein Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/04

CPC classification number: H01L29/7833 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract translation: 提供了包括源漏应力源的半导体器件及其制造方法。 所述方法可以包括在栅极图案侧的基板中形成凹陷区域，并且凹部区域的内表面可以包括（100）晶面的第一表面和{111}晶体之一的第二表面 飞机 该方法还可以包括执行第一选择性外延生长（SEG）工艺，以在约50托至约300托的范围内的工艺压力下在凹陷区的内表面上形成基底外延图案。 该方法还可以包括执行第二选择性外延生长（SEG）工艺以在基底外延图案上形成体外延图案。

公开(公告)号：US09136176B2

公开(公告)日：2015-09-15

申请号：US14318957

申请日：2014-06-30

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Myungsun Kim ,  Hoi Sung Chung

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66636

Abstract: A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Abstract translation: 制造一个或多个半导体器件的方法包括在半导体衬底中形成沟槽，执行循环过程以从沟槽去除污染物，以及在沟槽上形成外延层。 循环过程包括将含有锗烷，氯化氢和氢的第一反应气体和含有氯化氢和氢的第二反应气体依次提供到半导体衬底上。

公开(公告)号：US20150179795A1

公开(公告)日：2015-06-25

申请号：US14626211

申请日：2015-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk KIM ,  Hoi Sung Chung ,  Dongsuk Shin ,  Naein Lee

IPC: H01L29/78 ,  H01L29/04

CPC classification number: H01L29/7833 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract translation: 提供了包括源漏应力源的半导体器件及其制造方法。 所述方法可以包括在栅极图案侧的基板中形成凹陷区域，并且凹部区域的内表面可以包括（100）晶面的第一表面和{111}晶体之一的第二表面 飞机 该方法还可以包括执行第一选择性外延生长（SEG）工艺，以在约50托至约300托的范围内的工艺压力下在凹陷区的内表面上形成基底外延图案。 该方法还可以包括执行第二选择性外延生长（SEG）工艺以在基底外延图案上形成体外延图案。

公开(公告)号：US10892263B2

公开(公告)日：2021-01-12

申请号：US16270865

申请日：2019-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi Sung Chung ,  Tae Sung Kang ,  Dong Suk Shin ,  Kong Soo Lee ,  Jun-Won Lee

IPC: H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/108 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L21/311 ,  H01L21/324 ,  H01L29/08 ,  H01L29/40 ,  H01L21/266 ,  H01L29/04

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.

公开(公告)号：US20150140747A1

公开(公告)日：2015-05-21

申请号：US14565922

申请日：2014-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Hoi Sung Chung ,  Naein Lee

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L21/823437 ,  H01L21/02636 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.

Abstract translation: 半导体器件包括设置在半导体衬底上的栅极图案，设置在形成在栅极图案侧的半导体衬底中的凹陷区域中的体外延图案，设置在整体外延图案上的插入外延图案和封盖外延 图案设置在插入物外延图案上。 本体外延图案具有为{111}晶面的上倾斜面，并且插入物外延图案包括促进插入物外延图案在上倾斜表面上的生长速率的特定元件。

公开(公告)号：US20140084350A1

公开(公告)日：2014-03-27

申请号：US14021469

申请日：2013-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Hoi Sung Chung ,  Naein Lee

IPC: H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/02636 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.

Abstract translation: 半导体器件包括设置在半导体衬底上的栅极图案，设置在形成在栅极图案侧的半导体衬底中的凹陷区域中的体外延图案，设置在整体外延图案上的插入外延图案和封盖外延 图案设置在插入物外延图案上。 本体外延图案具有为{111}晶面的上倾斜面，并且插入物外延图案包括促进插入物外延图案在上倾斜表面上的生长速率的特定元件。

公开(公告)号：US09178060B2

公开(公告)日：2015-11-03

申请号：US14562937

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Hyuk Kim ,  Hoi Sung Chung ,  Myungsun Kim ,  Dongsuk Shin

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7834 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer.

Abstract translation: MOS晶体管包括在彼此间隔开的基板中形成的一对杂质区，以及形成在位于该对杂质区之间的基板的区域上的栅电极。 每个杂质区由第一外延层，第一外延层上的第二外延层和第二外延层上的第三外延层形成。 第一外延层由堆叠在每个第一子外延层上的至少一个第一子外延层和相应的第二子外延层形成。 第一子外延层的杂质浓度小于第二子外延层的杂质浓度。