公开(公告)号：US11232986B2

公开(公告)日：2022-01-25

申请号：US16785732

申请日：2020-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Yong Bae ,  Hoon Seok Seo ,  Ki Hyun Park ,  Hak-Sun Lee

IPC: H01L21/768

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

公开(公告)号：US11876017B2

公开(公告)日：2024-01-16

申请号：US17551357

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Yong Bae ,  Hoon Seok Seo ,  Ki Hyun Park ,  Hak-Sun Lee

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76885

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

公开(公告)号：US11075160B2

公开(公告)日：2021-07-27

申请号：US16385188

申请日：2019-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hwan Park ,  Seong Ho Park ,  Kyoung Pil Park ,  Tae Yong Bae ,  Eun-Chul Seo

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.

公开(公告)号：US20220108920A1

公开(公告)日：2022-04-07

申请号：US17551357

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Yong Bae ,  Hoon Seok Seo ,  Ki Hyun Park ,  Hak-Sun Lee

IPC: H01L21/768

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

公开(公告)号：US20200013715A1

公开(公告)日：2020-01-09

申请号：US16385188

申请日：2019-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hwan Park ,  Seong Ho Park ,  Kyoung Pil Park ,  Tae Yong Bae ,  Eun-Chul Seo

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.