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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12142607B2

    公开(公告)日：2024-11-12

    申请号：US17713834

    申请日：2022-04-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Cheol Kim ,  Dongkwon Kim ,  Hyunho Jung

    IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: A semiconductor device includes first and second active regions parallel to each other and respectively extending in a first direction, an isolation layer between the first and second active regions, a first line structure and a second line structure overlapping the first and second active regions and the isolation layer, parallel to each other, and extending in a second direction, a first source/drain region on the first active region, and a second source/drain region on the second active region. The first line structure includes a first gate structure, a second gate structure, and a first insulating separation pattern between the first and second gate structures. The second line structure includes a third gate structure, a fourth gate structure, and a second insulating separation pattern between the third and fourth gate structures. The first and second insulating separation patterns are spaced apart from each other. The first insulating separation pattern has first and second side surfaces opposing each other, and third and fourth side surfaces opposing each other. At least one of the first and second side surfaces and at least one of the third and fourth side surfaces have different side profiles.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230005910A1

    公开(公告)日：2023-01-05

    申请号：US17694192

    申请日：2022-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junmo Park ,  Yeonho Park ,  Kyubong Choi ,  Cheol Kim ,  Junseok Lee ,  Jinseok Lee

    IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

    Abstract: A semiconductor memory device includes: a substrate having a first channel structure and a second channel structure respectively extending in a first direction and arranged in a second direction perpendicular to the first direction; a first gate structure disposed on the first channel structure and extending in the second direction on the substrate; a second gate structure disposed on the second channel structure and extending in the second direction; first source/drain regions respectively disposed on opposite sides of the first gate structure; second source/drain regions respectively disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the first and second gate structures and having an upper surface at a level lower than that of an upper surface of each of the first and second gate structures, the gate separation pattern including a first insulating material; and a gate capping layer disposed on the first and second gate structures and having an extension portion extending between the first and second gate structures to be connected to the gate separation pattern, the gate capping layer including a second insulating material different from the first insulating material.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220376046A1

    公开(公告)日：2022-11-24

    申请号：US17648155

    申请日：2022-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Cheol Kim ,  Jeong Yeon Seo ,  Dong Kwon Kim ,  Hyun Ho Jung

    IPC: H01L29/06

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first active pattern, which extends in a first direction on the substrate, a second active pattern, which extends in the first direction on the substrate and is spaced apart from the first active pattern by a first pitch in a second direction different from the first horizontal direction, a third active pattern, which extends in the first direction on the substrate and is spaced apart from the second active pattern by a second pitch greater than the first pitch in the second direction, a field insulating layer, which borders side walls of each of the first to third active patterns, a dam, which is between the first active pattern and the second active pattern on the field insulating layer, the region between the second active pattern and the third active pattern being free of the dam, a gate electrode, which extends in the second direction, and has a first portion on the first active pattern, a second portion on the second active pattern, and a third portion on the third active pattern, a first work function layer between the first portion of the gate electrode and the dam, and a second work function layer between the second portion of the gate electrode and the dam.

    Memory device to correct defect cell generated after packaging
    6.
    发明授权
    Memory device to correct defect cell generated after packaging 有权
    内存装置纠正包装后产生的缺陷细胞

    公开(公告)号：US09455047B2

    公开(公告)日：2016-09-27

    申请号：US13799967

    申请日：2013-03-13

    Applicant: SAMSUNG Electronics Co., Ltd.

    Inventor： Cheol Kim ,  Sang-ho Shin ,  Jung-sik Kim

    IPC: G11C29/04 ,  G11C29/00 ,  G11C29/44

    CPC classification number: G11C29/04 ,  G11C29/4401 ,  G11C29/783 ,  G11C29/785 ,  G11C29/787 ,  G11C2029/4402

    Abstract: A memory device to correct a defect cell generated after packing is performed includes a memory cell array in which a plurality of memory cells are arranged, a repair circuit unit including a first storage unit to store defect cell information in the memory cell array, and a fuse circuit unit including a second storage unit that is programmed according to the defect cell information stored in the first storage unit. The first storage unit includes a volatile memory device, and the second storage unit includes a non-volatile memory device.

    Abstract translation: 用于校正打包后产生的缺陷单元的存储装置包括其中布置多个存储单元的存储单元阵列，包括存储单元阵列中的缺陷单元信息的第一存储单元的修复电路单元，以及 熔丝电路单元，包括根据存储在第一存储单元中的缺陷单元信息编程的第二存储单元。 第一存储单元包括易失性存储器件，并且第二存储单元包括非易失性存储器件。

    Field effect transistor having fin base and at lease one fin protruding from fin base
    9.
    发明授权
    Field effect transistor having fin base and at lease one fin protruding from fin base 有权
    场效应晶体管具有翅片基底和至少一个翅片从翅片基部突出

    公开(公告)号：US08987836B2

    公开(公告)日：2015-03-24

    申请号：US13780855

    申请日：2013-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeong-cheol Kim ,  Cheol Kim ,  Jaehun Seo ,  YooJung Lee ,  Kisoo Chang ,  Siyoung Choi

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/336

    CPC classification number: H01L29/785 ,  H01L29/7851

    Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

    Abstract translation: 场效应晶体管，其包括基板上的源极区域和漏极区域，从基板的顶面突出的翅片基板，从翅片基部向上延伸并将源极区域与漏极区域连接的多个翅片部， 翅片部分上的电极，以及翅片部分和栅电极之间的栅极电介质。 基板的顶面可以包括多个凹槽（例如，多个凸部和多个凹部）。 此外，可以设置器件隔离层以暴露多个翅片部分的上部并覆盖多个凹槽的顶表面。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230028875A1

    公开(公告)日：2023-01-26

    申请号：US17683589

    申请日：2022-03-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Cheol Kim ,  Jongchul Park

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a gate electrode including a first gate electrode on the first active pattern and a second gate electrode on the second active pattern, a gate cutting pattern between the first and second gate electrodes, gate spacers on opposing side surfaces of the gate electrode, and a gate capping pattern on top surfaces of the gate electrode, the gate cutting pattern, and the gate spacers and extending in the first direction. The gate cutting pattern includes a first and second side surfaces, which are opposite to each other in a second direction crossing the first direction. The first and side surfaces are in contact with respective ones of the gate spacers, and the top surface of the gate cutting pattern is closer to the substrate than the top surfaces of the pair of gate spacers.

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