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    FinFETs and the methods for forming the same
    51.
    发明授权
    FinFETs and the methods for forming the same 有权
    FinFET及其形成方法

    公开(公告)号：US09379217B2

    公开(公告)日：2016-06-28

    申请号：US14258615

    申请日：2014-04-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

    IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

    CPC分类号： H01L29/7848 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    摘要： A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.

    摘要翻译： 一种方法包括提供彼此平行的多个半导体鳍片，并且包括两个边缘鳍片和两个边缘鳍片之间的中心鳍片。 蚀刻两个边缘翅片中的每一个的中间部分，并且中心翅片不被蚀刻。 栅极电介质形成在中心翅片的顶表面和侧壁上。 在栅极电介质上形成栅电极。 两个边缘翅片的端部和中心翅片的端部是凹进的。 进行外延以形成外延区域，其中由两个边缘翅片的端部留下的空间生长的外延材料与从中心翅片的端部留下的空间生长的外延材料合并，形成外延 地区。 源极/漏极区域形成在外延区域中。

    MEMORY ARRAY STRUCTURE
    55.
    发明公开
    MEMORY ARRAY STRUCTURE 审中-公开

    公开(公告)号：US20240021226A1

    公开(公告)日：2024-01-18

    申请号：US17863201

    申请日：2022-07-12

    申请人： Taiwan Semiconductor Manufacturing Company Ltd.

    发明人： Hung-Li Chiang ,  Jer-Fu Wang ,  Tzu-Chiang Chen ,  Meng-Fan Chang

    IPC分类号： G11C7/16 ,  G11C7/10 ,  G11C13/00

    CPC分类号： G11C7/16 ,  G11C7/1006 ,  G11C13/003 ,  G11C2213/77

    摘要： In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    56.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20230361217A1

    公开(公告)日：2023-11-09

    申请号：US18352230

    申请日：2023-07-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chao-Ching Cheng ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen

    IPC分类号： H01L29/786 ,  H01L29/66

    CPC分类号： H01L29/78675 ,  H01L29/66757 ,  H01L29/78684

    摘要： A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.