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    CONTINUOUS PLANE OF THIN-FILM MATERIALS FOR A TWO-TERMINAL CROSS-POINT MEMORY
    53.
    发明申请
    CONTINUOUS PLANE OF THIN-FILM MATERIALS FOR A TWO-TERMINAL CROSS-POINT MEMORY 审中-公开
    连续两面终端薄膜材料的薄膜材料

    公开(公告)号：US20120292585A1

    公开(公告)日：2012-11-22

    申请号：US13566584

    申请日：2012-08-03

    Applicant: Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

    Inventor： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

    IPC: H01L47/00 ,  H01L21/02

    CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165

    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

    Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
    54.
    发明授权
    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
    本地位线及其选择方法可以访问交叉点阵列中的存储器元件

    公开(公告)号：US08270193B2

    公开(公告)日：2012-09-18

    申请号：US12657911

    申请日：2010-01-29

    Applicant: Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

    Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

    IPC: G11C5/02

    CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

    Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

    Abstract translation: 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

    Continuous plane of thin-film materials for a two-terminal cross-point memory
    55.
    发明授权
    Continuous plane of thin-film materials for a two-terminal cross-point memory 有权
    用于两端交叉点存储器的薄膜材料的连续平面

    公开(公告)号：US08237142B2

    公开(公告)日：2012-08-07

    申请号：US12932642

    申请日：2011-03-01

    Applicant: Robin Cheung ,  Jonathan Bornstein ,  David Hansen ,  Travis Byonghyop Oh ,  Darrell Rinerson

    Inventor： Robin Cheung ,  Jonathan Bornstein ,  David Hansen ,  Travis Byonghyop Oh ,  Darrell Rinerson

    IPC: H01L29/02 ,  H01L29/06

    CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165

    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

    Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

    Memory Device Using Ion Implant Isolated Conductive Metal Oxide
    58.
    发明申请
    Memory Device Using Ion Implant Isolated Conductive Metal Oxide 有权
    使用离子注入隔离导电金属氧化物的存储器件

    公开(公告)号：US20110315948A1

    公开(公告)日：2011-12-29

    申请号：US13215895

    申请日：2011-08-23

    Applicant: DARRELL RINERSON ,  JONATHAN BORNSTEIN ,  DAVID HANSEN ,  ROBIN CHEUNG ,  STEVEN W. LONGCOR ,  RENE MEYER ,  LAWRENCE SCHLOSS

    Inventor： DARRELL RINERSON ,  JONATHAN BORNSTEIN ,  DAVID HANSEN ,  ROBIN CHEUNG ,  STEVEN W. LONGCOR ,  RENE MEYER ,  LAWRENCE SCHLOSS

    IPC: H01L45/00 ,  B82Y99/00

    CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

    Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
    60.
    发明申请
    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
    本地位线及其选择方法可以访问交叉点阵列中的存储器元件

    公开(公告)号：US20110188281A1

    公开(公告)日：2011-08-04

    申请号：US12657911

    申请日：2010-01-29

    Applicant: Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Namala

    Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Namala

    IPC: G11C5/02 ,  G11C11/00 ,  G11C8/00 ,  H01L21/82

    CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

    Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

    Abstract translation: 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

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