公开(公告)号：US20140008798A1

公开(公告)日：2014-01-09

申请号：US14006614

申请日：2011-03-22

Applicant: Shinji Baba ,  Masaki Watanabe ,  Muneharu Tokunaga ,  Kazuyuki Nakagawa

Inventor： Shinji Baba ,  Masaki Watanabe ,  Muneharu Tokunaga ,  Kazuyuki Nakagawa

IPC: H01L23/498

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/1134 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，作为安装有半导体芯片的布线基板，不使用积层布线板，而是使用贯通布线板THWB。 以这种方式，在本发明中，仅使用芯层形成的贯通布线板，因此不需要考虑堆积层与芯层之间的热膨胀系数的差异， 不需要考虑由于积聚层不存在而在积层中形成的精细通孔的电断开。 结果，根据本发明，可以提高半导体器件的可靠性，同时降低成本。

公开(公告)号：US20130256895A1

公开(公告)日：2013-10-03

申请号：US13436124

申请日：2012-03-30

Applicant: Michael Su ,  Bryan Black ,  Joe Siegel ,  Neil McLellan ,  Michael Alfano

Inventor： Michael Su ,  Bryan Black ,  Joe Siegel ,  Neil McLellan ,  Michael Alfano

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/10 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14136 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/29076 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of manufacturing is provided that includes fabricating a first set of interconnect structures on a side of a first semiconductor substrate. The first semiconductor substrate is operable to have at least one of plural semiconductor substrates stacked on the side. The first set of interconnect structures is arranged in a pattern. Each of the plural semiconductor substrates has a second set of interconnect structures arranged in the pattern, one of the plural semiconductor substrates has a smallest footprint of the plural semiconductor substrates. The pattern has a footprint smaller than the smallest footprint of the plural semiconductor substrates.

Abstract translation: 提供一种制造方法，其包括在第一半导体衬底的侧面上制造第一组互连结构。 第一半导体衬底可操作以具有堆叠在一侧的多个半导体衬底中的至少一个。 第一组互连结构以图案布置。 多个半导体衬底中的每一个具有以图案布置的第二组互连结构，多个半导体衬底中的一个半导体衬底的占用面积最小。 该图案的占地面积小于多个半导体衬底的最小占地面积。

公开(公告)号：US08530345B2

公开(公告)日：2013-09-10

申请号：US13765280

申请日：2013-02-12

Applicant: International Business Machines Corporation

Inventor： David Justin West ,  David John Russell

IPC: H01L21/44

CPC classification number: H01L21/02697 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/1132 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16238 ,  H01L2224/17515 ,  H01L2224/17517 ,  H01L2224/81141 ,  H01L2224/81194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/131 ,  H01L2924/00

Abstract: An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

公开(公告)号：US20130062741A1

公开(公告)日：2013-03-14

申请号：US13228757

申请日：2011-09-09

Applicant: Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Ming-Da Cheng

Inventor： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Ming-Da Cheng

IPC: H01L23/495 ,  H01L21/60 ,  H01L21/98 ,  H01L23/488

CPC classification number: H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/13014 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2224/14136 ,  H01L2224/14145 ,  H01L2224/14156 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

Abstract translation: 公开了半导体器件及其制造和封装方法。 在一个实施例中，半导体器件包括集成电路和耦合到集成电路的表面的多个铜柱。 多个铜柱具有细长的形状。 多个铜柱中的至少50％以大致向心的方向排列。

公开(公告)号：US08361598B2

公开(公告)日：2013-01-29

申请号：US12985456

申请日：2011-01-06

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: B32B3/10 ,  B32B5/12 ,  H01L23/485 ,  H01L23/488

CPC classification number: H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/14136 ,  H01L2224/26152 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/4921 ,  Y10T29/49222 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24347 ,  Y10T428/24479 ,  Y10T428/24529 ,  Y10T428/24545 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.

Abstract translation: 一种电气结构和成型方法。 电结构包括第一衬底，第一介电层，底部填充层，第一焊料结构和第二衬底。 第一介电层形成在第一基板的顶表面上。 第一电介质层包括延伸穿过所述第一电介质层的顶表面和底表面的第一开口。 第一焊料结构形成在第一开口内以及在所述第一介电层的顶表面的一部分之上。 第二衬底形成在底部填充层上并与底部填充层接触。

公开(公告)号：US20120313133A1

公开(公告)日：2012-12-13

申请号：US13224607

申请日：2011-09-02

Applicant: KUAN-NENG CHEN ,  CHENG-TA KO ,  WEI-CHUNG LO

Inventor： KUAN-NENG CHEN ,  CHENG-TA KO ,  WEI-CHUNG LO

IPC: H01L33/62 ,  H01L33/48

CPC classification number: H01L33/62 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/167 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/17517 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00013 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A heterostructure contains an IC and an LED. An IC and an LED are initially provided. The IC has at least one first electric-conduction block and at least one first connection block. The IC electrically connects with the first electric-conduction block. The first face of the LED has at least one second electric-conduction block and at least one second connection block. The LED electrically connects to the second electric-conduction block. Subsequently, the first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block. The first electric-conduction block is electrically connected with the second electric-conduction block and forms a heterostructure. The system simultaneously provides functions of heat radiation and electric communication for the IC and LED resulting in a high-density, multifunctional heterostructure.

Abstract translation: 异质结构包含IC和LED。 最初提供IC和LED。 IC具有至少一个第一导电块和至少一个第一连接块。 IC与第一导电块电连接。 LED的第一面具有至少一个第二导电块和至少一个第二连接块。 LED电连接到第二导电块。 随后，第一导电块和第一连接块分别连接到第二导电块和第二连接块。 第一导电块与第二导电块电连接并形成异质结构。 该系统同时提供IC和LED的散热和电通信功能，从而产生高密度多功能异质结构。

公开(公告)号：US20120299197A1

公开(公告)日：2012-11-29

申请号：US13478613

申请日：2012-05-23

Applicant: Heungkyu KWON ,  Kang Joon Lee ,  Jae Wook Yoo ,  Su-Chang Lee

Inventor： Heungkyu KWON ,  Kang Joon Lee ,  Jae Wook Yoo ,  Su-Chang Lee

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/13 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3157 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13561 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13649 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/1751 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract translation: 半导体封装包括包括中心部分和周边部分的第一基板，附接到第一基板的中心部分的至少一个第一中心连接部件和附接到第一基板的周边部分的至少一个第一周边连接部件。 第一中心连接构件包括第一支撑件和围绕第一支撑件的第一融合导电层。

公开(公告)号：US07989959B1

公开(公告)日：2011-08-02

申请号：US12361827

申请日：2009-01-29

Applicant: Arifur Rahman

Inventor： Arifur Rahman

IPC: H01L23/42 ,  H01L21/44

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/481 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06132 ,  H01L2224/06519 ,  H01L2224/14132 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stacked-die integrated circuit and a method of fabricating same. The stacked-die integrated circuit has circuitry formed in the first surface of a mother die, a plurality of through-die vias with at least one through-die via providing electrical connection between the circuitry of the mother die and the second surface and a plurality of contact pads formed in the second surface of the semiconductor die for mounting a daughter die wherein some of the contact pads are electrically isolated dummy pads.

Abstract translation: 堆叠管芯集成电路及其制造方法。 堆叠管芯集成电路具有形成在母模的第一表面中的电路，具有至少一个通孔的多个通孔通孔，其通过在母模的电路和第二表面之间提供电连接，以及多个 形成在半导体管芯的第二表面中的用于安装子管芯的接触焊盘，其中一些接触焊盘是电隔离的假焊盘。

公开(公告)号：US20090110881A1

公开(公告)日：2009-04-30

申请号：US11924662

申请日：2007-10-26

Applicant: Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: B32B3/10 ,  B05D5/12

CPC classification number: H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/14136 ,  H01L2224/26152 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/4921 ,  Y10T29/49222 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24347 ,  Y10T428/24479 ,  Y10T428/24529 ,  Y10T428/24545 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, first dielectric layer, an underfill layer, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The underfill layer is formed over the top surface of the first dielectric layer and within the first opening. The second substrate is formed over and in contact with the underfill layer.

Abstract translation: 一种电气结构和成型方法。 电结构包括第一衬底，第一介电层，底部填充层和第二衬底。 第一介电层形成在第一基板的顶表面上。 第一电介质层包括延伸穿过所述第一电介质层的顶表面和底表面的第一开口。 底部填充层形成在第一介电层的顶表面上并且在第一开口内。 第二衬底形成在底部填充层上并与底部填充层接触。

公开(公告)号：US06680544B2

公开(公告)日：2004-01-20

申请号：US10061247

申请日：2002-02-04

Applicant: Hsueh-Chung Shelton Lu ,  Kenny Chang ,  Jimmy Huang

Inventor： Hsueh-Chung Shelton Lu ,  Kenny Chang ,  Jimmy Huang

IPC: H01L2940

CPC classification number: H01L24/14 ,  H01L23/50 ,  H01L23/64 ,  H01L24/02 ,  H01L2224/0235 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/45144 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/48

Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract translation: 公开了倒装芯片的凸块布置。 所述凸块布置包括：形成在所述倒装芯片的芯区域处的导电凸块阵列，围绕所述导电凸块阵列的第一环导电凸块，围绕所述第一环的第二环，围绕所述第二环的第三环，以及 围绕第三环的第四环。 在四个凸起环中，第三环和第四环的凸起彼此交错，其大部分设置为I / O信号端子，以减少用于I / O信号连接的长度导电迹线。 第一和第二环中的凸块被提供用于电源连接或接地连接。 核心区域的第一环，第二环，第三环，第四环和凸起通过再分配层连接到互连层的导电迹线。 再分配层位于钝化层和互连层之间。