Patent search ap:"Heungkyu KWON" Page 1

1.

发明授权
Semiconductor package including stacked memory chips 有权
Title translation: 半导体封装包括堆叠式存储芯片

公开(公告)号：US09214441B2

公开(公告)日：2015-12-15

申请号：US14283833

申请日：2014-05-21

Applicant: Heungkyu Kwon , Kyoungmook Lim

Inventor： Heungkyu Kwon , Kyoungmook Lim

IPC: H01L23/48 , H01L23/00 , H01L25/065 , H01L25/10

CPC classification number: H01L24/30 , H01L24/06 , H01L24/73 , H01L25/0652 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05571 , H01L2224/06131 , H01L2224/06134 , H01L2224/06155 , H01L2224/14131 , H01L2224/14134 , H01L2224/16225 , H01L2224/16227 , H01L2224/26175 , H01L2224/29036 , H01L2224/3001 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/13099 , H01L2924/00011 , H01L2224/45099

Abstract: According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively. The first and second jumper chips are spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction. The second semiconductor package may include a second package substrate and a logic chip on the second package substrate. The first semiconductor package may be on the second semiconductor package.

Abstract translation: 根据示例性实施例，半导体封装包括第一和第二半导体封装。第一半导体封装包括第一封装衬底，在第一方向上在第一封装衬底上彼此间隔开的第一和第二存储器芯片，分别在第一和第二存储器芯片上的第三和第四存储器芯片，以及第一和第二跳线分别在第一和第二存储器芯片上的芯片。第一和第二跳线芯片分别与第三和第四存储器芯片在与第一方向交叉的第二方向上分开。第二半导体封装可以包括第二封装衬底和第二封装衬底上的逻辑芯片。第一半导体封装可以在第二半导体封装上。

2.

发明申请
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权
Title translation: 半导体封装及其制造方法

公开(公告)号：US20110042797A1

公开(公告)日：2011-02-24

申请号：US12857928

申请日：2010-08-17

Applicant: Ji-hyun Park , Heungkyu Kwon , Min-Ok Na , Taehwan Kim

Inventor： Ji-hyun Park , Heungkyu Kwon , Min-Ok Na , Taehwan Kim

IPC: H01L23/00 , H01L23/488 , H01L23/498

CPC classification number: H01L21/56 , H01L21/563 , H01L23/13 , H01L23/3128 , H01L23/3142 , H01L25/0657 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/26175 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83051 , H01L2224/83385 , H01L2225/1023 , H01L2225/1058 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/15331 , H01L2924/00

Abstract: A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.

Abstract translation: 半导体封装包括具有绝缘层的衬底。绝缘层具有第一表面粗糙度的第一区域和具有第二表面粗糙度的第二区域。半导体芯片安装在第一区域中，底部填充树脂溶液填充到半导体芯片和绝缘层之间的空间中。第二区域的粗糙度防止底部填充树脂从半导体芯片流出，从而减小半导体封装的尺寸。

3.

发明申请
PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开

公开(公告)号：US20170194299A1

公开(公告)日：2017-07-06

申请号：US15392275

申请日：2016-12-28

Applicant: Heungkyu KWON

Inventor： Heungkyu KWON

IPC: H01L25/10 , H01L23/544 , H01L25/00

CPC classification number: H01L25/105 , H01L23/544 , H01L25/50 , H01L2223/54406 , H01L2223/5442 , H01L2223/54426 , H01L2223/54433 , H01L2223/54486 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/00014

Abstract: Provided are a package-on-package type semiconductor package and a method of fabricating the same. The semiconductor package includes upper package stacked on a lower package and a via provided between the lower and upper packages to electrically connect the lower and upper packages to each other. The lower package includes a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer encapsulating the lower semiconductor chip and including an alignment mark. The lower mold layer includes a marking region, which is provided between the via and the lower semiconductor chip, and on which the alignment mark is provided.

4.

发明授权
Surface temperature management method of mobile device and memory thermal management method of multichip package 有权

公开(公告)号：US09606591B2

公开(公告)日：2017-03-28

申请号：US13617619

申请日：2012-09-14

Applicant: Heungkyu Kwon , Jae Choon Kim , Eunseok Cho , Jichul Kim

Inventor： Heungkyu Kwon , Jae Choon Kim , Eunseok Cho , Jichul Kim

IPC: G06F1/20

CPC classification number: G06F1/206 , G01J5/10 , G05B15/02

Abstract: A surface temperature management method of mobile device is provided. The method includes sensing a temperature of an application processor in an operation mode of the mobile device; and controlling the application processor using the sensed temperature and a surface temperature management table to manage a surface temperature of a target part of the mobile device. The surface temperature management table includes information related to the temperature of the application processor corresponding to the surface temperature of the target part in the operation mode.

5.

发明授权
Semiconductor packages including a metal layer between first and second semiconductor chips 有权
Title translation: 包括第一和第二半导体芯片之间的金属层的半导体封装

公开(公告)号：US09390992B2

公开(公告)日：2016-07-12

申请号：US14289814

申请日：2014-05-29

Applicant: Heungkyu Kwon , Sangho An

Inventor： Heungkyu Kwon , Sangho An

IPC: H01L23/13 , H01L23/31 , H01L23/498 , H01L23/552 , H01L25/065 , H01L25/10 , H01L23/00

CPC classification number: H01L23/3128 , H01L23/49816 , H01L23/552 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06537 , H01L2225/06568 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/12042 , H01L2924/15153 , H01L2924/15156 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012 , H01L2924/0665 , H01L2924/00 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: Semiconductor packages are provided. A semiconductor package may include a wiring board and a first semiconductor chip on the wiring board. Moreover, the semiconductor package may include a metal layer on the first semiconductor chip and a second semiconductor chip on the metal layer. The metal layer may be between the first and second semiconductor chips.

Abstract translation: 提供半导体封装。半导体封装可以包括布线板和布线板上的第一半导体芯片。此外，半导体封装可以包括第一半导体芯片上的金属层和金属层上的第二半导体芯片。金属层可以在第一和第二半导体芯片之间。

6.

发明申请
SEMICONDUCTOR PACKAGE 有权
Title translation: 半导体封装

公开(公告)号：US20150048521A1

公开(公告)日：2015-02-19

申请号：US14283833

申请日：2014-05-21

Applicant: Heungkyu KWON , Kyoungmook LIM

Inventor： Heungkyu KWON , Kyoungmook LIM

IPC: H01L23/00

CPC classification number: H01L24/30 , H01L24/06 , H01L24/73 , H01L25/0652 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05571 , H01L2224/06131 , H01L2224/06134 , H01L2224/06155 , H01L2224/14131 , H01L2224/14134 , H01L2224/16225 , H01L2224/16227 , H01L2224/26175 , H01L2224/29036 , H01L2224/3001 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/13099 , H01L2924/00011 , H01L2224/45099

Abstract: According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively. The first and second jumper chips are spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction. The second semiconductor package may include a second package substrate and a logic chip on the second package substrate. The first semiconductor package may be on the second semiconductor package.

Abstract translation: 根据示例性实施例，半导体封装包括第一和第二半导体封装。第一半导体封装包括第一封装衬底，在第一方向上在第一封装衬底上彼此间隔开的第一和第二存储器芯片，分别在第一和第二存储器芯片上的第三和第四存储器芯片，以及第一和第二跳线分别在第一和第二存储器芯片上的芯片。第一和第二跳线芯片分别与第三和第四存储器芯片在与第一方向交叉的第二方向上分开。第二半导体封装可以包括第二封装衬底和第二封装衬底上的逻辑芯片。第一半导体封装可以在第二半导体封装上。

7.

发明授权
Method of forming a semiconductor package 有权
Title translation: 形成半导体封装的方法

公开(公告)号：US08709879B2

公开(公告)日：2014-04-29

申请号：US13835683

申请日：2013-03-15

Applicant: Ji-hyun Park , Heungkyu Kwon , Min-Ok Na , Taehwan Kim

Inventor： Ji-hyun Park , Heungkyu Kwon , Min-Ok Na , Taehwan Kim

IPC: H01L21/56

CPC classification number: H01L21/56 , H01L21/563 , H01L23/13 , H01L23/3128 , H01L23/3142 , H01L25/0657 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/26175 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83051 , H01L2224/83385 , H01L2225/1023 , H01L2225/1058 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/15331 , H01L2924/00

Abstract: A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.

Abstract translation: 半导体封装包括具有绝缘层的衬底。绝缘层具有第一表面粗糙度的第一区域和具有第二表面粗糙度的第二区域。半导体芯片安装在第一区域中，底部填充树脂溶液填充到半导体芯片和绝缘层之间的空间中。第二区域的粗糙度防止底部填充树脂从半导体芯片流出，从而减小半导体封装的尺寸。

8.

发明申请
CHIP USING TRIPLE PAD CONFIGURATION AND PACKAGING METHOD THEREOF 有权
Title translation: 芯片使用三重垫片配置及其包装方法

公开(公告)号：US20160133585A1

公开(公告)日：2016-05-12

申请号：US14843326

申请日：2015-09-02

Applicant: HEUNGKYU KWON , INHYUK KIM

Inventor： HEUNGKYU KWON , INHYUK KIM

IPC: H01L23/00 , H01L21/683 , G06F21/30 , H01L21/66

CPC classification number: H01L24/05 , G06F21/30 , H01L21/561 , H01L21/568 , H01L22/32 , H01L23/3114 , H01L23/3128 , H01L23/3192 , H01L24/03 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/48 , H01L24/85 , H01L25/0657 , H01L2224/0231 , H01L2224/0237 , H01L2224/02375 , H01L2224/02381 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05024 , H01L2224/05548 , H01L2224/06515 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06568 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00 , H01L2924/014

Abstract: A chip includes a core layer, at least one redistribution layer formed on the core layer, and at least one triple pad connected to a pad of the core layer through the at least one redistribution layer or at least one via connected to the at least one redistribution layer. The at least one triple pad includes a bonding pad, a redistribution layer pad connected to the at least one redistribution layer, and a test pad configured to perform a wafer level test. The bonding pad, the redistribution layer pad and the test pad are connected to one another through the at least one redistribution layer, and the test pad is disposed in a core area that overlaps the core layer.

Abstract translation: 芯片包括核心层，在芯层上形成的至少一个再分布层，以及至少一个三重焊盘，其通过至少一个再分布层或连接至该至少一个的至少一个通孔连接到芯层的焊盘再分配层。所述至少一个三重衬垫包括接合焊盘，连接到所述至少一个再分布层的再分配层焊盘以及被配置为执行晶片级测试的测试焊盘。接合焊盘，再分布层焊盘和测试焊盘通过至少一个再分配层彼此连接，并且测试焊盘设置在与芯层重叠的芯区域中。