Invention Application
US20160133585A1 CHIP USING TRIPLE PAD CONFIGURATION AND PACKAGING METHOD THEREOF
有权
芯片使用三重垫片配置及其包装方法
- Patent Title: CHIP USING TRIPLE PAD CONFIGURATION AND PACKAGING METHOD THEREOF
- Patent Title (中): 芯片使用三重垫片配置及其包装方法
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Application No.: US14843326Application Date: 2015-09-02
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Publication No.: US20160133585A1Publication Date: 2016-05-12
- Inventor: HEUNGKYU KWON , INHYUK KIM
- Applicant: HEUNGKYU KWON , INHYUK KIM
- Priority: KR10-2014-0155555 20141110
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/683 ; G06F21/30 ; H01L21/66
Abstract:
A chip includes a core layer, at least one redistribution layer formed on the core layer, and at least one triple pad connected to a pad of the core layer through the at least one redistribution layer or at least one via connected to the at least one redistribution layer. The at least one triple pad includes a bonding pad, a redistribution layer pad connected to the at least one redistribution layer, and a test pad configured to perform a wafer level test. The bonding pad, the redistribution layer pad and the test pad are connected to one another through the at least one redistribution layer, and the test pad is disposed in a core area that overlaps the core layer.
Public/Granted literature
- US09859237B2 Chip using triple pad configuration and packaging method thereof Public/Granted day:2018-01-02
Information query
IPC分类:
