公开(公告)号：US20170278842A1

公开(公告)日：2017-09-28

申请号：US15081702

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.

公开(公告)号：US20170221884A1

公开(公告)日：2017-08-03

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/42392

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US20170170268A1

公开(公告)日：2017-06-15

申请号：US15367320

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Peijie Feng ,  Kern Rim ,  Jeffrey Junhao Xu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L21/324 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/78696

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure having rounded nanowire structures is disclosed. To reduce the distance between adjacent nanowire structures to reduce parasitic capacitance while providing sufficient gate control of the channel, the nanowire channel structure employs rounded nanowire structures. For example, the rounded nanowire structures provide for a decreased height from a center area of the rounded nanowire structures to end areas of the rounded nanowire structures. Gate material is disposed around rounded ends of the rounded nanowire structures to extend into a portion of separation areas between adjacent nanowire structures. The gate material extends in the separation areas between adjacent nanowire structures sufficient to create a fringing field to the channel where gate material is not adjacently disposed, to provide strong gate control of the channel even though gate material does not completely surround the rounded nanowire structures.

公开(公告)号：US20170110374A1

公开(公告)日：2017-04-20

申请号：US15198763

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L21/823821 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/823431 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

公开(公告)号：US09620612B2

公开(公告)日：2017-04-11

申请号：US14625974

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Xia Li

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L27/08 ,  H01L27/088 ,  H01L21/28 ,  H01L27/11592 ,  G11C11/22

CPC classification number: H01L29/66833 ,  G11C11/221 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/324 ,  H01L27/088 ,  H01L27/11568 ,  H01L27/11592 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78 ,  H01L29/785

Abstract: An integrated circuit device includes a first transistor structure formed in a memory region (e.g., an embedded memory region) of a die. The first transistor structure includes a substrate (e.g., a planar substrate of a planar FET or a fin of a FinFET) and a first gate. The first gate includes a dipole layer proximate to the substrate and a barrier layer proximate to the dipole layer. The integrated circuit device further includes a second transistor structure formed in a logic device region of the die. The second transistor structure includes a second gate that includes an interface layer, a dielectric layer, and a cap layer. The dielectric layer is formed between the cap layer and the interface layer.

公开(公告)号：US09502283B2

公开(公告)日：2016-11-22

申请号：US14627653

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang ,  Choh Fei Yeap

IPC: H01L21/768 ,  G06F17/50 ,  H01L21/311 ,  H01L23/535 ,  G03F1/00 ,  G03F7/20

CPC classification number: H01L21/76802 ,  G03F1/14 ,  G03F7/203 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/7045 ,  G03F7/70466 ,  G06F17/5077 ,  H01L21/31116 ,  H01L23/535

Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.

Abstract translation: 公开了基于电子束（e-beam）的半导体器件特征。 在特定方面，一种方法包括执行第一光刻工艺以在半导体器件上制造第一组切割图案特征。 从特征到有效区域的第一组切割图案特征的每个特征的距离大于或等于阈值距离。 该方法还包括执行电子束（e-beam）工艺以在半导体器件上制造第二切割图案特征。 第二切割图案特征从第二切割图案特征到有效区域的第二距离小于或等于阈值距离。

公开(公告)号：US20160172456A1

公开(公告)日：2016-06-16

申请号：US14567925

申请日：2014-12-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Bin Yang ,  Jun Yuan ,  Yu Lu

IPC: H01L29/417 ,  H01L21/283

CPC classification number: H01L29/41775 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a transistor having a metal gate, a source, and a drain. The semiconductor device also includes a high resistance metal etch-stop layer positioned above the metal gate of the transistor. The semiconductor device also includes a metal layer formed on the high resistance metal etch-stop layer. The metal layer is positioned above at least one of the source of the transistor or the drain of the transistor.

Abstract translation: 半导体器件包括具有金属栅极，源极和漏极的晶体管。 半导体器件还包括位于晶体管的金属栅极上方的高电阻金属蚀刻停止层。 半导体器件还包括形成在高电阻金属蚀刻停止层上的金属层。 金属层位于晶体管的源极或晶体管的漏极中的至少一个的上方。

公开(公告)号：US20160126144A1

公开(公告)日：2016-05-05

申请号：US14991882

申请日：2016-01-08

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L21/823814 ,  C23C14/24 ,  C23C14/54 ,  C23C16/46 ,  C23C16/52 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66568

Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

公开(公告)号：US09257556B2

公开(公告)日：2016-02-09

申请号：US14269981

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Vladimir Machkaoutsan ,  Kern Rim ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract translation: 形成FinFET器件的半导体鳍片的方法包括在半导体鳍片上共形沉积硅 - 锗（SiGe）的非晶或多晶薄膜。 该方法还包括氧化非晶或多晶薄膜以将锗从非晶或多晶薄膜扩散到半导体鳍中。 这种方法还包括去除非晶或多晶薄膜的氧化部分。

公开(公告)号：US10141305B2

公开(公告)日：2018-11-27

申请号：US15266214

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Haining Yang ,  Jun Yuan ,  Kern Rim ,  Periannan Chidambaram

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L29/78

Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.