公开(公告)号：US10818567B2

公开(公告)日：2020-10-27

申请号：US16358203

申请日：2019-03-19

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Ryohei Urata ,  Teckgyu Kang

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

公开(公告)号：US20200296862A1

公开(公告)日：2020-09-17

申请号：US16890103

申请日：2020-06-02

Applicant: Google LLC

Inventor： Madhusudan Krishnan Iyengar ,  Christopher Gregory Malone ,  Yuan Li ,  Jorge Padilla ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Norman Paul Jouppi

IPC: H05K7/20

Abstract: A server tray package includes a motherboard assembly that includes a plurality of data center electronic devices, the plurality of data center electronic devices including at least one heat generating processor device; and a liquid cold plate assembly. The liquid cold plate assembly includes a base portion mounted to the motherboard assembly, the base portion and motherboard assembly defining a volume that at least partially encloses the plurality of data center electronic devices; and a top portion mounted to the base portion and including a heat transfer member shaped to thermally contact the heat generating processor device, the heat transfer member including an inlet port and an outlet port that are in fluid communication with a cooling liquid flow path defined through the heat transfer member.

公开(公告)号：US20200098715A1

公开(公告)日：2020-03-26

申请号：US16698482

申请日：2019-11-27

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L23/00 ,  H05K1/11 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/14

Abstract: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

公开(公告)号：US10515920B2

公开(公告)日：2019-12-24

申请号：US15948456

申请日：2018-04-09

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L23/02 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

公开(公告)号：US20240347414A1

公开(公告)日：2024-10-17

申请号：US18634198

申请日：2024-04-12

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H01L23/373 ,  H01L23/00 ,  H01L25/065 ,  H05K3/34 ,  H05K7/20

CPC classification number: H01L23/3732 ,  H01L23/562 ,  H01L24/32 ,  H01L24/83 ,  H05K3/3436 ,  H05K7/20254 ,  H01L25/0655 ,  H01L2223/58 ,  H01L2224/32 ,  H01L2224/32245 ,  H01L2924/15311 ,  H05K2201/10378 ,  H05K2203/041

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US20240250082A1

公开(公告)日：2024-07-25

申请号：US18624411

申请日：2024-04-02

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

公开(公告)号：US11978721B2

公开(公告)日：2024-05-07

申请号：US17579012

申请日：2022-01-19

Applicant: Google LLC

Inventor： Woon-Seong Kwon ,  Namhoon Kim ,  Teckgyu Kang ,  Ryohei Urata

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/04 ,  H01L25/075 ,  H01L31/12 ,  H10K39/00

CPC classification number: H01L25/0652 ,  G02B6/4257 ,  H01L23/3121 ,  H01L23/3672 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/162 ,  H01L25/041 ,  H01L25/075 ,  H01L25/167 ,  H01L31/12 ,  H01L2225/06517 ,  H10K39/601

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

公开(公告)号：US11967538B2

公开(公告)日：2024-04-23

申请号：US17226177

申请日：2021-04-09

Applicant: Google LLC

Inventor： Woon-Seong Kwon ,  Xiaojin Wei ,  Madhusudan K. Iyengar ,  Teckgyu Kang

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/1433 ,  H01L2924/1434

Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may be formed as an integral part of an IC die that may assist temperature control of the IC die when in operation. The temperature control element may include a heat dissipation material disposed therein to assist dissipating thermal energy generated by the plurality of devices in the IC die during operation.

公开(公告)号：US11955406B2

公开(公告)日：2024-04-09

申请号：US17570647

申请日：2022-01-07

Applicant: Google LLC

Inventor： Yingying Wang ,  Emad Samadiani ,  Madhusudan K. Iyengar ,  Padam Jain ,  Xiaojin Wei ,  Teckgyu Kang ,  Sudharshan Sugavanesh Udhayakumar ,  Yingshi Tang

IPC: H01L23/46 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/46 ,  H01L21/56 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/29035 ,  H01L2224/32221 ,  H01L2224/73253

Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may assist temperature control of the IC die when in operation. In one example, the temperature control element may have a plurality of thermal dissipating features disposed on a first surface of the IC die to efficiently control and dissipate the thermal energy from the IC die when in operation. A second surface opposite to the first surface of the IC die may include a plurality of devices, such as semiconductors transistors, devices, electrical components, circuits, or the like, that may generate thermal energy when in operation. The temperature control element may provide an IC die with high efficiency of heat dissipation that is suitable for 3D IC package structures and requirements.

公开(公告)号：US20230402430A1

公开(公告)日：2023-12-14

申请号：US18239368

申请日：2023-08-29

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.