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    Active Silicon D2D Bridge
    1.
    发明公开
    Active Silicon D2D Bridge 审中-公开

    公开(公告)号：US20230411297A1

    公开(公告)日：2023-12-21

    申请号：US17841188

    申请日：2022-06-15

    Applicant: Google LLC

    Inventor： Georgios Konstadinidis ,  Woon-Seong Kwon ,  Jaesik Lee ,  Teckgyu Kang ,  Jin Y. Kim ,  Sukalpa Biswas ,  Biao He ,  Yujeong Shim

    IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00

    CPC classification number: H01L23/5381 ,  H01L25/0655 ,  H01L25/18 ,  H01L23/5384 ,  H01L23/5385 ,  H01L21/4853 ,  H01L21/486 ,  H01L25/50

    Abstract: A microelectronic system may include a substrate having a first surface, one or more interposers mounted to and electrically connected to the first surface, first and second application specific integrated circuits (ASICs) each at least partially overlying and electrically connected to one of the interposers, a plurality of high-bandwidth memory elements (HBMs) each at least partially overlying and electrically connected to one of the interposers, and an active silicon bridge mounted to and electrically connected to the first surface and providing an electrical connection between the first and second ASICs, the active silicon bridge having active microelectronic devices therein. The microelectronic system may be configured such that the first and second ASICs and the active silicon bridge each have a purely digital CMOS interface therein. A plurality of bumps providing the electrical connection between the ASICs and the active silicon bridge may be configured to receive serial data therethrough.

    Integrated circuit package for high bandwidth memory
    2.
    发明授权
    Integrated circuit package for high bandwidth memory 有权

    公开(公告)号：US11488944B2

    公开(公告)日：2022-11-01

    申请号：US17157278

    申请日：2021-01-25

    Applicant: Google LLC

    Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

    Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

    Backside Integrated Voltage Regulator For Integrated Circuits
    3.
    发明申请
    Backside Integrated Voltage Regulator For Integrated Circuits 有权

    公开(公告)号：US20250006706A1

    公开(公告)日：2025-01-02

    申请号：US18823093

    申请日：2024-09-03

    Applicant: Google LLC

    Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

    IPC: H01L25/065

    Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

    Multi-Directional Sharing And Multiplexing For High Bandwidth Memory
    8.
    发明申请
    Multi-Directional Sharing And Multiplexing For High Bandwidth Memory 有权

    公开(公告)号：US20250139027A1

    公开(公告)日：2025-05-01

    申请号：US18923025

    申请日：2024-10-22

    Applicant: Google LLC

    Inventor： Horia Alexandru Toma ,  Rahul Nagarajan ,  Yujeong Shim ,  Rammohan Padmanabhan

    IPC: G06F13/16 ,  G06F13/40

    Abstract: Generally disclosed herein are electronic circuits with high bandwidth interfaces (HBI) for multi-directional die-to-die communications. The HBIs are designed to allow for sharing of data between all sides of the memory chiplets. By using all sides of the memory chiplets and multiplexing the data between the multiple connected chiplets, the total bandwidth of the memory available to the connected chiplets can increase. The sharing and multiplexing of the data can also be dynamically configured to accommodate various options for the allocation of performance levels and the associated cost.

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