公开(公告)号：US12051679B2

公开(公告)日：2024-07-30

申请号：US17121868

申请日：2020-12-15

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang

IPC: H01L25/10 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L23/49883 ,  H01L2225/1052 ,  H01L2225/107

Abstract: The technology relates to an integrated circuit (IC) package in which an interconnection interface chiplet and/or interconnection interface circuit are relocated, partitioned, and/or decoupled from a main or core IC die and/or high-bandwidth memory (HBM) components in an integrated component package.

公开(公告)号：US20250006706A1

公开(公告)日：2025-01-02

申请号：US18823093

申请日：2024-09-03

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US20220238504A1

公开(公告)日：2022-07-28

申请号：US17157278

申请日：2021-01-25

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

公开(公告)号：US20220157787A1

公开(公告)日：2022-05-19

申请号：US17667104

申请日：2022-02-08

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US11264358B2

公开(公告)日：2022-03-01

申请号：US16567766

申请日：2019-09-11

Applicant: Google LLC

Inventor： Woon-Seong Kwon ,  Namhoon Kim ,  Teckgyu Kang ,  Ryohei Urata

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/04 ,  H01L25/075 ,  H01L31/12

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

公开(公告)号：US11488944B2

公开(公告)日：2022-11-01

申请号：US17157278

申请日：2021-01-25

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

公开(公告)号：US20220189934A1

公开(公告)日：2022-06-16

申请号：US17121868

申请日：2020-12-15

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang

IPC: H01L25/10 ,  H01L23/498

Abstract: The technology relates to an integrated circuit (IC) package in which an interconnection interface chiplet and/or interconnection interface circuit are relocated, partitioned, and/or decoupled from a main or core IC die and/or high-bandwidth memory (HBM) components in an integrated component package.

公开(公告)号：US12278217B2

公开(公告)日：2025-04-15

申请号：US18823093

申请日：2024-09-03

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US20210074677A1

公开(公告)日：2021-03-11

申请号：US16567766

申请日：2019-09-11

Applicant: Google LLC

Inventor： Woon-Seong Kwon ,  Namhoon Kim ,  Teckgyu Kang ,  Ryohei Urata

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/538 ,  H01L23/498

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

公开(公告)号：US11978721B2

公开(公告)日：2024-05-07

申请号：US17579012

申请日：2022-01-19

Applicant: Google LLC

Inventor： Woon-Seong Kwon ,  Namhoon Kim ,  Teckgyu Kang ,  Ryohei Urata

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/04 ,  H01L25/075 ,  H01L31/12 ,  H10K39/00

CPC classification number: H01L25/0652 ,  G02B6/4257 ,  H01L23/3121 ,  H01L23/3672 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/162 ,  H01L25/041 ,  H01L25/075 ,  H01L25/167 ,  H01L31/12 ,  H01L2225/06517 ,  H10K39/601

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.