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    Dynamic Power-Aware Workload Scheduler
    1.
    发明申请
    Dynamic Power-Aware Workload Scheduler 有权

    公开(公告)号：US20250103128A1

    公开(公告)日：2025-03-27

    申请号：US18371012

    申请日：2023-09-21

    Applicant: Google LLC

    Inventor： Houle Gan ,  Madhusudan K. Iyengar ,  Michael David Hutton

    IPC: G06F1/329

    Abstract: Systems and methods for managing power allocation by connecting a power capping control loop to a workload scheduler. The work scheduler may receive a workload for execution by one or more of a plurality of machines, assign the workload to one or more designated machines of the plurality of machines, determine a respective power quota for each of the one or more designated machines, instruct a programmable power capping control loop to control operation of each of the one or more designated machines according to its respective power quota; and update, after assigning the workload to the one or more designated machines, a record indicating (i) available power of a domain including the plurality of machines and/or (ii) available machines within the domain.

    Programmable System TDP With ASIC Power Capping
    2.
    发明申请
    Programmable System TDP With ASIC Power Capping 有权

    公开(公告)号：US20220057823A1

    公开(公告)日：2022-02-24

    申请号：US16996405

    申请日：2020-08-18

    Applicant: Google LLC

    Inventor： Robert Ashby Armistead, III ,  Shuai Jiang ,  Binayak Roy ,  Thomas James Norrie ,  Houle Gan

    IPC: G05F1/575

    Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.

    POWER THROTTLING MECHANISM USING INSTRUCTION RATE LIMITING IN HIGH POWER MACHINE-LEARNING ASICs
    6.
    发明申请
    POWER THROTTLING MECHANISM USING INSTRUCTION RATE LIMITING IN HIGH POWER MACHINE-LEARNING ASICs 有权

    公开(公告)号：US20210286419A1

    公开(公告)日：2021-09-16

    申请号：US16818493

    申请日：2020-03-13

    Applicant: Google LLC

    Inventor： Houle Gan ,  Thomas James Norrie ,  Gregory Sizikov ,  Georgios Konstadinidis

    IPC: G06F1/28 ,  G06N20/00

    Abstract: A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.

    POWER MODULES WITH ELEVATED INDUCTORS AND CAPACITORS ARRANGED UNDER THE INDUCTORS
    7.
    发明公开
    POWER MODULES WITH ELEVATED INDUCTORS AND CAPACITORS ARRANGED UNDER THE INDUCTORS 审中-公开

    公开(公告)号：US20240203630A1

    公开(公告)日：2024-06-20

    申请号：US18590577

    申请日：2024-02-28

    Applicant: Google LLC

    Inventor： Houle Gan ,  Shuai Jiang ,  Gregory Sizikov ,  Xin Li ,  Chee Yee Chung

    IPC: H01F17/00 ,  H05K5/00

    CPC classification number: H01F17/0006 ,  H05K5/0069

    Abstract: The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.

    Power modules with elevated inductors and capacitors arranged under the inductors
    9.
    发明授权
    Power modules with elevated inductors and capacitors arranged under the inductors 有权

    公开(公告)号：US11948716B1

    公开(公告)日：2024-04-02

    申请号：US16800776

    申请日：2020-02-25

    Applicant: Google LLC

    Inventor： Houle Gan ,  Shuai Jiang ,  Gregory Sizikov ,  Xin Li ,  Chee Yee Chung

    IPC: H01F17/00 ,  H01F27/24 ,  H01F27/28 ,  H01F27/29 ,  H05K5/00

    CPC classification number: H01F17/0006 ,  H05K5/0069

    Abstract: The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.

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