公开(公告)号：US12278217B2

公开(公告)日：2025-04-15

申请号：US18823093

申请日：2024-09-03

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US20210294411A1

公开(公告)日：2021-09-23

申请号：US17340878

申请日：2021-06-07

Applicant: Google LLC

Inventor： Mikhail Popovich ,  Gregory Sizikov

IPC: G06F1/3296 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If no failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

公开(公告)号：US20240094264A1

公开(公告)日：2024-03-21

申请号：US17885071

申请日：2022-08-10

Applicant: Google LLC

Inventor： Ali Eltoukhy ,  Mikhail Popovich ,  Rami Abouhamze

IPC: G01R19/00 ,  G01R31/26 ,  H02J7/00

CPC classification number: G01R19/0084 ,  G01R31/26 ,  H02J7/0047

Abstract: A voltage supervisor (VS) or voltage sensing circuitry or architecture that can detect fast voltage transients. To detect fast voltage transients, a dedicated differential pair is routed between a point of load, such as a die or other chip, processor, etc., and the circuitry of the voltage supervisor. By connecting the differential pair at the point of load, fast voltage transients may be detected at the load level (e.g., at the point of load) and thereafter used to enable, disable, and/or restart an electronic device, such as a die, chip, processor, or other electronic component or system.

公开(公告)号：US20230402430A1

公开(公告)日：2023-12-14

申请号：US18239368

申请日：2023-08-29

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US11830855B2

公开(公告)日：2023-11-28

申请号：US17667104

申请日：2022-02-08

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US20210249384A1

公开(公告)日：2021-08-12

申请号：US16788994

申请日：2020-02-12

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US20250006706A1

公开(公告)日：2025-01-02

申请号：US18823093

申请日：2024-09-03

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US11435818B2

公开(公告)日：2022-09-06

申请号：US17340878

申请日：2021-06-07

Applicant: Google LLC

Inventor： Mikhail Popovich ,  Gregory Sizikov

IPC: G06F1/3296 ,  G06F1/10 ,  G06F1/06 ,  G06F1/08

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If no failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

公开(公告)号：US20220157787A1

公开(公告)日：2022-05-19

申请号：US17667104

申请日：2022-02-08

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US11276668B2

公开(公告)日：2022-03-15

申请号：US16788994

申请日：2020-02-12

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.