公开(公告)号：US10658322B2

公开(公告)日：2020-05-19

申请号：US16698482

申请日：2019-11-27

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538 ,  H01L25/18 ,  H05K1/11 ,  H01L23/14

Abstract: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

公开(公告)号：US10818567B2

公开(公告)日：2020-10-27

申请号：US16358203

申请日：2019-03-19

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Ryohei Urata ,  Teckgyu Kang

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

公开(公告)号：US20200098715A1

公开(公告)日：2020-03-26

申请号：US16698482

申请日：2019-11-27

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L23/00 ,  H05K1/11 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/14

Abstract: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

公开(公告)号：US10515920B2

公开(公告)日：2019-12-24

申请号：US15948456

申请日：2018-04-09

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L23/02 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

公开(公告)号：US11264295B2

公开(公告)日：2022-03-01

申请号：US17038878

申请日：2020-09-30

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Ryohei Urata ,  Teckgyu Kang

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

公开(公告)号：US20200161235A1

公开(公告)日：2020-05-21

申请号：US16358197

申请日：2019-03-19

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L23/522 ,  H01L49/02

Abstract: A processor assembly and a system including a processor assembly are disclosed. The processor assembly includes an interposer disposed on a substrate, an integrated circuit disposed on the interposer, a memory circuit disposed on the interposer and coupled to the integrated circuit, and a capacitor embedded in the interposer. The capacitor includes at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure. The capacitor includes a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit. The capacitor includes a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit. The capacitor includes an oxide layer electrically isolating the capacitor from the interposer.

公开(公告)号：US10257921B1

公开(公告)日：2019-04-09

申请号：US15951717

申请日：2018-04-12

Applicant: Google LLC

Inventor： Richard Roy ,  Pierre-luc Cantin ,  Teckgyu Kang ,  Woon Seong Kwon

IPC: H05K1/02 ,  H01P3/08

Abstract: Embedded air gap transmission lines and methods of fabrication are provided. An apparatus having an air gap transmission line can include a first conductive plane, a core dielectric layer having a bottom surface in contact with the first conductive plane, a conductor having a bottom surface in contact with a top surface of the core dielectric layer, and a second conductive plane positioned over, and spaced apart from, a top surface of the conductor such that a gap separates the conductor from the second conductive plane. The top surface of the conductor is separated from the bottom surface of the second conductive plane by a first distance measured along an axis normal to the first conductive plane, and the bottom surface of the conductor is separated from the first conductive plane by a second distance greater than the first distance measured along the axis.

公开(公告)号：US10083920B1

公开(公告)日：2018-09-25

申请号：US15886246

申请日：2018-02-01

Applicant: Google LLC

Inventor： William Edwards ,  Erick Tuttle ,  Madhusudan Krishnan Iyengar ,  Yuan Li ,  Jorge Padilla ,  Woon Seong Kwon ,  TeckGyu Kang

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/00 ,  H05K5/00 ,  H01L23/50 ,  H05K5/02

CPC classification number: H01L23/562 ,  H01L23/04 ,  H01L23/16 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/50 ,  H05K5/0026 ,  H05K5/0217

Abstract: The subject matter of this specification generally relates to electronic packages. In some implementations, a lidless electronic package includes a substrate having a surface and a die disposed on the surface of the substrate. The die has an outside perimeter, a bottom surface adjacent to the surface of the substrate, and a top surface. The electronic package includes a stiffener disposed on the surface of the substrate. The stiffener includes a first surface that is a first distance from the surface of the substrate and a second surface disposed between the die and the first surface. The first distance is greater than a distance between the surface of the substrate and the top surface of the die. The second surface is a second distance from the surface of the substrate that is less than the distance between the surface of the substrate and the top surface of the die.

公开(公告)号：US11276668B2

公开(公告)日：2022-03-15

申请号：US16788994

申请日：2020-02-12

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US10930592B2

公开(公告)日：2021-02-23

申请号：US16405304

申请日：2019-05-07

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Teckgyu Kang

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/56 ,  H01L49/02 ,  H01L25/16 ,  H01L23/48 ,  H01L23/31

Abstract: A packaged assembly and a method of producing the packaged assembly is disclosed. The packaged assembly includes a redistribution layer (RDL), an integrated circuit (IC), one or more memory modules, and an interposer comprising a plurality of vias from a list of through-silicon-vias (TSVs), through-mold-via (TMVs), and plated-through-hold-via (PTHs). In some implementations, the IC is electrically and mechanically attached to a first side of the RDL. In some implementations, the one or more memory modules and the interposer are disposed on a second side of the RDL. The packaged assembly also includes a mold having a mold material encapsulating the IC, the one or more memory modules, the interposer, and the RDL to form the packaged assembly. In some implementations, the IC is electrically conductively connected an external circuit board via a series of electrical connections between the IC, the RDL, the vias, and the external circuit board.