公开(公告)号：US12274079B2

公开(公告)日：2025-04-08

申请号：US18244716

申请日：2023-09-11

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Teckgyu Kang ,  Scott Lee Kirkman ,  Woon-Seong Kwon

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/16 ,  H10D1/68

Abstract: This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.

公开(公告)号：US12051679B2

公开(公告)日：2024-07-30

申请号：US17121868

申请日：2020-12-15

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Teckgyu Kang

IPC: H01L25/10 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L23/49883 ,  H01L2225/1052 ,  H01L2225/107

Abstract: The technology relates to an integrated circuit (IC) package in which an interconnection interface chiplet and/or interconnection interface circuit are relocated, partitioned, and/or decoupled from a main or core IC die and/or high-bandwidth memory (HBM) components in an integrated component package.

公开(公告)号：US11990386B2

公开(公告)日：2024-05-21

申请号：US17333570

申请日：2021-05-28

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H01L23/00 ,  H01L23/373 ,  H05K3/34 ,  H05K7/20 ,  H01L25/065

CPC classification number: H01L23/3732 ,  H01L23/562 ,  H01L24/32 ,  H01L24/83 ,  H05K3/3436 ,  H05K7/20254 ,  H01L25/0655 ,  H01L2223/58 ,  H01L2224/32 ,  H01L2224/32245 ,  H01L2924/15311 ,  H05K2201/10378 ,  H05K2203/041

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US20230420494A1

公开(公告)日：2023-12-28

申请号：US18244716

申请日：2023-09-11

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Teckgyu Kang ,  Scott Lee Kirkman ,  Woon-Seong Kwon

IPC: H10N69/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L28/90 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19102

Abstract: This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.

公开(公告)号：US20200273777A1

公开(公告)日：2020-08-27

申请号：US16286406

申请日：2019-02-26

Applicant: Google LLC

Inventor： Padam Jain ,  Yuan Li ,  Teckgyu Kang ,  Madhusudan Iyengar

IPC: H01L23/473 ,  H01L23/367 ,  H01L23/373 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H05K7/20

Abstract: A device for direct liquid cooling is disclosed. The device includes a packaged assembly disposed on a substrate. The device also includes a metal channel layer having a plurality of channels disposed on top of the packaged assembly, and a top seal disposed on the metal channel layer. The top seal has at least one inlet and at least one outlet for direct liquid cooling. The metal channel layer includes copper or silver. The packaged assembly can also include silicon channels. In addition, the method of producing the device is also disclosed.

公开(公告)号：US10658322B2

公开(公告)日：2020-05-19

申请号：US16698482

申请日：2019-11-27

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538 ,  H01L25/18 ,  H05K1/11 ,  H01L23/14

Abstract: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

公开(公告)号：US10548240B1

公开(公告)日：2020-01-28

申请号：US16246013

申请日：2019-01-11

Applicant: Google LLC

Inventor： Madhusudan Krishnan Iyengar ,  Christopher Gregory Malone ,  Yuan Li ,  Jorge Padilla ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Norman Paul Jouppi

IPC: H05K7/20 ,  F28F3/02 ,  H01L23/473

Abstract: A server tray package includes a motherboard assembly that includes a plurality of data center electronic devices; and a liquid cold plate assembly. The liquid cold plate assembly includes a base portion mounted to the motherboard assembly, the base portion and motherboard assembly defining a volume that at least partially encloses the plurality of data center electronic devices; and a top portion mounted to the base portion and including a heat transfer member that includes a first number of inlet ports and a second number of outlet ports that are in fluid communication with a cooling liquid flow path defined through the heat transfer member, the first number of inlet ports being different that the second number of outlet ports.

公开(公告)号：US10548239B1

公开(公告)日：2020-01-28

申请号：US16167905

申请日：2018-10-23

Applicant: Google LLC

Inventor： Madhusudan Krishnan Iyengar ,  Gregory Sizikov ,  Yuan Li ,  Jorge Padilla ,  Woon-Seong Kwon ,  Teckgyu Kang

IPC: H05K7/20 ,  H05K7/14

Abstract: A cooling system, for example, for rack mounted electronic devices (e.g., servers, processors, memory, networking devices or otherwise) in a data center. In various disclosed implementations, the cooling system may be or include a liquid cold plate assembly that is part of or integrated with a server tray package. In some implementations, the liquid cold plate assembly includes a base portion and a top portion that, in combination, form a cooling liquid flow path through which a cooling liquid is circulated and a thermal interface between one or more heat generating devices and the cooling liquid.

公开(公告)号：US12243802B2

公开(公告)日：2025-03-04

申请号：US18634198

申请日：2024-04-12

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H01L23/00 ,  B23K1/00 ,  H01L23/373 ,  H05K3/34 ,  H05K7/20 ,  H01L25/065

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US20250006706A1

公开(公告)日：2025-01-02

申请号：US18823093

申请日：2024-09-03

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.