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公开(公告)号：US12243802B2
公开(公告)日：2025-03-04
申请号：US18634198
申请日：2024-04-12
Applicant: Google LLC
Inventor： Madhusudan K. Iyengar , Christopher Malone , Woon-Seong Kwon , Emad Samadiani , Melanie Beauchemin , Padam Jain , Teckgyu Kang , Yuan Li , Connor Burgess , Norman Paul Jouppi , Nicholas Stevens-Yu , Yingying Wang
IPC: H01L23/00 , B23K1/00 , H01L23/373 , H05K3/34 , H05K7/20 , H01L25/065
Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.
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公开(公告)号：US11990386B2
公开(公告)日：2024-05-21
申请号：US17333570
申请日：2021-05-28
Applicant: Google LLC
Inventor： Madhusudan K. Iyengar , Christopher Malone , Woon-Seong Kwon , Emad Samadiani , Melanie Beauchemin , Padam Jain , Teckgyu Kang , Yuan Li , Connor Burgess , Norman Paul Jouppi , Nicholas Stevens-Yu , Yingying Wang
IPC: H01L23/00 , H01L23/373 , H05K3/34 , H05K7/20 , H01L25/065
CPC classification number: H01L23/3732 , H01L23/562 , H01L24/32 , H01L24/83 , H05K3/3436 , H05K7/20254 , H01L25/0655 , H01L2223/58 , H01L2224/32 , H01L2224/32245 , H01L2924/15311 , H05K2201/10378 , H05K2203/041
Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.
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3.发明公开公开(公告)号：US20240121931A1
公开(公告)日：2024-04-11
申请号：US18225944
申请日：2023-07-25
Applicant: Google LLC
Inventor： Yingshi Tang , Yingying Wang , Padam Jain , Emad Samadiani , Sudharshan Sugavanesh Udhayakumar , Madhusudan K. Iyengar
CPC classification number: H05K13/0409 , H05K1/0203 , H05K7/20509
Abstract: Methods and structures for providing thermal dissipating elements on integrated circuit (“IC”) dies are disclosed. A thermal dissipating element placement assembly, such as a pin fin placement assembly, along with a vacuum pickup assembly, can be used to assist with simultaneous placement of multiple pin fins with desired profiles on desired locations of the IC die. The pin fin placement assembly may be comprised of one or more plates with a plurality of apertures therein for receiving the pin fins. The pin fin placement assembly can be further incorporated into a thermal cooling structure, which can include a manifold configured to encase the IC die and attached pin fins.
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公开(公告)号：US20240347414A1
公开(公告)日：2024-10-17
申请号：US18634198
申请日：2024-04-12
Applicant: Google LLC
Inventor： Madhusudan K. Iyengar , Christopher Malone , Woon-Seong Kwon , Emad Samadiani , Melanie Beauchemin , Padam Jain , Teckgyu Kang , Yuan Li , Connor Burgess , Norman Paul Jouppi , Nicholas Stevens-Yu , Yingying Wang
IPC: H01L23/373 , H01L23/00 , H01L25/065 , H05K3/34 , H05K7/20
CPC classification number: H01L23/3732 , H01L23/562 , H01L24/32 , H01L24/83 , H05K3/3436 , H05K7/20254 , H01L25/0655 , H01L2223/58 , H01L2224/32 , H01L2224/32245 , H01L2924/15311 , H05K2201/10378 , H05K2203/041
Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.
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Patent Agency Ranking
公开(公告)号：US11955406B2
公开(公告)日：2024-04-09
申请号：US17570647
申请日：2022-01-07
Applicant: Google LLC
Inventor： Yingying Wang , Emad Samadiani , Madhusudan K. Iyengar , Padam Jain , Xiaojin Wei , Teckgyu Kang , Sudharshan Sugavanesh Udhayakumar , Yingshi Tang
CPC classification number: H01L23/46 , H01L21/56 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/29035 , H01L2224/32221 , H01L2224/73253
Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may assist temperature control of the IC die when in operation. In one example, the temperature control element may have a plurality of thermal dissipating features disposed on a first surface of the IC die to efficiently control and dissipate the thermal energy from the IC die when in operation. A second surface opposite to the first surface of the IC die may include a plurality of devices, such as semiconductors transistors, devices, electrical components, circuits, or the like, that may generate thermal energy when in operation. The temperature control element may provide an IC die with high efficiency of heat dissipation that is suitable for 3D IC package structures and requirements.
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公开(公告)号：US20250102746A1
公开(公告)日：2025-03-27
申请号：US18372989
申请日：2023-09-26
Applicant: Google LLC
Inventor： Horia Alexandru Toma , Zuowei Shen , Ilyas Mohammed , Yingying Wang , William F. Edwards, Jr.
Abstract: The technology generally relates to high bandwidth memory (HBM) packages and processor packages that have optical connectivity. Disclosed systems and methods herein allow for HBM dies that are interconnected with an optical interface in a manner that allows for compact, high-performance computing. An HBM package can be cooled using a cooling unit that is distinct from the processor package. In addition, the cooling unit can be configured so as to provide thermal contact with a subset of high-power components within the HBM package.
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公开(公告)号：US20210378106A1
公开(公告)日：2021-12-02
申请号：US17333570
申请日：2021-05-28
Applicant: Google LLC
Inventor： Madhusudan K. Iyengar , Christopher Malone , Woon-Seong Kwon , Emad Samadiani , Melanie Beauchemin , Padam Jain , Teckgyu Kang , Yuan Li , Connor Burgess , Norman Paul Jouppi , Nicholas Stevens-Yu , Yingying Wang
Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.
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8.发明公开公开(公告)号：US20240038620A1
公开(公告)日：2024-02-01
申请号：US17876813
申请日：2022-07-29
Applicant: Google LLC
Inventor： Yingshi Tang , Yingying Wang , Padam Jain , Emad Samadiani , Sudharshan Sugavanesh Udhayakumar , Madhusudan K. Iyengar
IPC: H01L23/367 , H01L23/467 , H01L23/31 , H01L23/00
CPC classification number: H01L23/3677 , H01L23/467 , H01L23/3128 , H01L24/18 , H01L2924/1811 , H01L2224/16227
Abstract: A pin fin placement assembly utilized to form pin fins in a thermal dissipating feature is provided. The pin fin placement assembly may place the pin fins on an IC die disposed in the IC package. The pin fin placement assembly may assist massively placing the pin fins with desired profiles and numbers on desired locations of the IC die. The plurality of pin fins is formed in a first plurality of apertures in the pin fin placement assembly. A thermal process is then performed to solder the plurality of pin fins on the IC die.
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公开(公告)号：US20230163048A1
公开(公告)日：2023-05-25
申请号：US17570647
申请日：2022-01-07
Applicant: Google LLC
Inventor： Yingying Wang , Emad Samadiani , Madhusudan K. Iyengar , Padam Jain , Xiaojin Wei , Teckgyu Kang , Sudharshan Sugavanesh Udhayakumar , Yingshi Tang
Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may assist temperature control of the IC die when in operation. In one example, the temperature control element may have a plurality of thermal dissipating features disposed on a first surface of the IC die to efficiently control and dissipate the thermal energy from the IC die when in operation. A second surface opposite to the first surface of the IC die may include a plurality of devices, such as semiconductors transistors, devices, electrical components, circuits, or the like, that may generate thermal energy when in operation. The temperature control element may provide an IC die with high efficiency of heat dissipation that is suitable for 3D IC package structures and requirements.
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