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    Backside Integrated Voltage Regulator For Integrated Circuits
    2.
    发明申请
    Backside Integrated Voltage Regulator For Integrated Circuits 有权

    公开(公告)号：US20250006706A1

    公开(公告)日：2025-01-02

    申请号：US18823093

    申请日：2024-09-03

    Applicant: Google LLC

    Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

    IPC: H01L25/065

    Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

    Methods and heat distribution devices for thermal management of chip assemblies
    3.
    发明授权
    Methods and heat distribution devices for thermal management of chip assemblies 有权

    公开(公告)号：US11600548B2

    公开(公告)日：2023-03-07

    申请号：US17333607

    申请日：2021-05-28

    Applicant: Google LLC

    Inventor： Woon-Seong Kwon ,  Yuan Li ,  Zhi Yang

    IPC: H01L23/373 ,  H01L23/00 ,  H05K3/34 ,  H05K7/20 ,  H01L25/065

    Abstract: According to an aspect of the disclosure, an example microelectronic device assembly includes a substrate, a microelectronic element electrically connected to the substrate, a stiffener element overlying the substrate, and a heat distribution device overlying the rear surface of the microelectronic element. The stiffener element may extend around the microelectronic element. The stiffener element may include a first material that has a first coefficient of thermal expansion (“CTE”). A surface of the stiffener element may face toward the heat distribution device. The heat distribution device may include a second material that has a second CTE. The first material may be different than the second material. The first CTE of the first material of the stiffener element may be greater than the second CTE of the second material of the heat distribution device.

    Methods And Heat Distribution Devices For Thermal Management Of Chip Assemblies
    7.
    发明申请
    Methods And Heat Distribution Devices For Thermal Management Of Chip Assemblies 有权

    公开(公告)号：US20210375715A1

    公开(公告)日：2021-12-02

    申请号：US17333607

    申请日：2021-05-28

    Applicant: Google LLC

    Inventor： Woon-Seong Kwon ,  Yuan Li ,  Zhi Yang

    IPC: H01L23/373 ,  H01L23/00

    Abstract: According to an aspect of the disclosure, an example microelectronic device assembly includes a substrate, a microelectronic element electrically connected to the substrate, a stiffener element overlying the substrate, and a heat distribution device overlying the rear surface of the microelectronic element. The stiffener element may extend around the microelectronic element. The stiffener element may include a first material that has a first coefficient of thermal expansion (“CTE”). A surface of the stiffener element may face toward the heat distribution device. The heat distribution device may include a second material that has a second CTE. The first material may be different than the second material. The first CTE of the first material of the stiffener element may be greater than the second CTE of the second material of the heat distribution device.

    Deep trench capacitors embedded in package substrate
    8.
    发明授权
    Deep trench capacitors embedded in package substrate 有权

    公开(公告)号：US12274079B2

    公开(公告)日：2025-04-08

    申请号：US18244716

    申请日：2023-09-11

    Applicant: Google LLC

    Inventor： Nam Hoon Kim ,  Teckgyu Kang ,  Scott Lee Kirkman ,  Woon-Seong Kwon

    IPC: H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/16 ,  H10D1/68

    Abstract: This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.

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