公开(公告)号：US11990386B2

公开(公告)日：2024-05-21

申请号：US17333570

申请日：2021-05-28

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H01L23/00 ,  H01L23/373 ,  H05K3/34 ,  H05K7/20 ,  H01L25/065

CPC classification number: H01L23/3732 ,  H01L23/562 ,  H01L24/32 ,  H01L24/83 ,  H05K3/3436 ,  H05K7/20254 ,  H01L25/0655 ,  H01L2223/58 ,  H01L2224/32 ,  H01L2224/32245 ,  H01L2924/15311 ,  H05K2201/10378 ,  H05K2203/041

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US11348859B2

公开(公告)日：2022-05-31

申请号：US16596100

申请日：2019-10-08

Applicant: Google LLC

Inventor： Melanie Beauchemin ,  Madhusudan Iyengar ,  Christopher Malone ,  Gregory Imwalle

IPC: H01L21/52 ,  H01L23/38 ,  H01L25/18 ,  H01L23/053 ,  H01L23/433 ,  H01L25/00 ,  H01L21/48 ,  F25B21/02 ,  H01L23/473

Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.

公开(公告)号：US20210378106A1

公开(公告)日：2021-12-02

申请号：US17333570

申请日：2021-05-28

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H05K3/34 ,  H05K7/20 ,  H01L23/00

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US20200035583A1

公开(公告)日：2020-01-30

申请号：US16596100

申请日：2019-10-08

Applicant: Google LLC

Inventor： Melanie Beauchemin ,  Madhusudan Iyengar ,  Christopher Malone ,  Gregory Imwalle

IPC: H01L23/38 ,  H01L25/18 ,  H01L23/053 ,  H01L23/433 ,  H01L25/00 ,  H01L21/52 ,  H01L21/48 ,  F25B21/02

Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.

公开(公告)号：US20190074237A1

公开(公告)日：2019-03-07

申请号：US15696962

申请日：2017-09-06

Applicant: Google LLC

Inventor： Melanie Beauchemin ,  Madhusudan Iyengar ,  Christopher Malone ,  Gregory Imwalle

IPC: H01L23/38 ,  H01L25/18 ,  H01L23/053 ,  H01L23/433 ,  H01L25/00 ,  H01L21/52 ,  H01L21/48 ,  F25B21/02

Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.

公开(公告)号：US12243802B2

公开(公告)日：2025-03-04

申请号：US18634198

申请日：2024-04-12

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H01L23/00 ,  B23K1/00 ,  H01L23/373 ,  H05K3/34 ,  H05K7/20 ,  H01L25/065

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US11895807B2

公开(公告)日：2024-02-06

申请号：US16885500

申请日：2020-05-28

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Melanie Beauchemin ,  Christopher Malone

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  H05K7/20 ,  H01M10/613

CPC classification number: H05K7/208 ,  H01M10/613 ,  H05K7/20936

Abstract: A data rack system includes a data center rack frame, a shelf positioned within the data center rack frame; and a modular battery unit disposed on the shelf. The modular battery unit further includes a housing having an outer surface, a plurality of strips of phase change material (“PCM”) attached to the outer surface and spaced apart from one another; and air flow channels. The air flow channels are formed in spaces between two adjacent strips of the plurality of strips and defined by a shape and size of the spaces between the two adjacent strips.

公开(公告)号：US20210378132A1

公开(公告)日：2021-12-02

申请号：US16885500

申请日：2020-05-28

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Melanie Beauchemin ,  Christopher Malone

IPC: H05K7/20 ,  H01M10/613

Abstract: A data rack system includes a data center rack frame, a shelf positioned within the data center rack frame; and a modular battery unit disposed on the shelf. The modular battery unit further includes a housing having an outer surface, a plurality of strips of phase change material (“PCM”) attached to the outer surface and spaced apart from one another; and air flow channels. The air flow channels are formed in spaces between two adjacent strips of the plurality of strips and defined by a shape and size of the spaces between the two adjacent strips.

公开(公告)号：US20240347414A1

公开(公告)日：2024-10-17

申请号：US18634198

申请日：2024-04-12

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H01L23/373 ,  H01L23/00 ,  H01L25/065 ,  H05K3/34 ,  H05K7/20

CPC classification number: H01L23/3732 ,  H01L23/562 ,  H01L24/32 ,  H01L24/83 ,  H05K3/3436 ,  H05K7/20254 ,  H01L25/0655 ,  H01L2223/58 ,  H01L2224/32 ,  H01L2224/32245 ,  H01L2924/15311 ,  H05K2201/10378 ,  H05K2203/041

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.