公开(公告)号：US20170194495A1

公开(公告)日：2017-07-06

申请号：US14984379

申请日：2015-12-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chii-Horng Ll ,  Chien-l KUO ,  Lilly SU ,  Chien-Chang SU ,  Yi-Kai TSENG ,  Ying-Wei LI

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L29/167 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L29/16

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/66575

摘要： A semiconductor device having n-type field-effect-transistor (NFET) structure and a method of fabricating the same are provided. The NFET structure of the semiconductor device includes a silicon substrate, at least one source/drain portion and a cap layer. The source/drain portion can be disposed within the silicon substrate, and the source/drain portion comprises at least one n-type dopant-containing portion. The cap layer overlies and covers the source/drain portion, and the cap layer includes silicon carbide (SiC) or silicon germanium (SiGe) with relatively low germanium concentration, thereby preventing n-type dopants in the at least one n-type dopant-containing portion of the source/drain portion from being degraded after sequent thermal and cleaning processes.

公开(公告)号：US20170186852A1

公开(公告)日：2017-06-29

申请号：US14981980

申请日：2015-12-29

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Xueming Dexter TAN ,  Kiok Boone Elgin QUEK ,  Xinfu LIU

IPC分类号： H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/66575 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/167 ,  H01L29/6659

摘要： A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

公开(公告)号：US20170186649A1

公开(公告)日：2017-06-29

申请号：US15461004

申请日：2017-03-16

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Makoto Yasuda ,  Taiji Ema ,  Mitsuaki Hori ,  Kazushi Fujita

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/28 ,  H01L21/66 ,  H01L21/02

CPC分类号： H01L21/823412 ,  H01L21/02238 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/84 ,  H01L22/12 ,  H01L22/20 ,  H01L27/088 ,  H01L27/11546 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/42324 ,  H01L29/66575 ,  H01L29/66825

摘要： A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.

公开(公告)号：US20170117387A1

公开(公告)日：2017-04-27

申请号：US14921434

申请日：2015-10-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC分类号： H01L29/66 ,  H01L21/225

CPC分类号： H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

摘要： The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

公开(公告)号：US09633849B2

公开(公告)日：2017-04-25

申请号：US15093867

申请日：2016-04-08

申请人： Texas Instruments Incorporated

发明人： Sameer P. Pendharkar ,  Binghua Hu

IPC分类号： H01L21/425 ,  H01L21/70 ,  H01L21/027 ,  H01L21/266 ,  H01L21/426 ,  H01L21/02 ,  H01L21/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/0274 ,  H01L21/02694 ,  H01L21/0271 ,  H01L21/266 ,  H01L21/32 ,  H01L21/426 ,  H01L21/823493 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.

公开(公告)号：US09601594B2

公开(公告)日：2017-03-21

申请号：US13295178

申请日：2011-11-14

申请人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/70 ,  H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/762

CPC分类号： H01L29/0847 ,  H01L21/76224 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.

公开(公告)号：US09576957B2

公开(公告)日：2017-02-21

申请号：US14729766

申请日：2015-06-03

申请人： International Business Machines Corporation

发明人： Praneet Adusumilli ,  Emre Alptekin ,  Kangguo Cheng ,  Balasubramanian Pranatharthiharan ,  Shom S. Ponoth

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66643

摘要： A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

摘要翻译： 半导体衬底包括较低的源极/漏极（S / D）区域。 在下部S / D区域之间的半导体衬底上布置有替代金属栅极（RMG）结构。 上升的S / D区域分别布置在与RMG结构相邻的下部S / D区域上。 升高的S / D区域可以凹入以形成接触沟槽。 第一自对准触点位于第一有效区域内的升高的S / D区域上，而第二自对准触点位于第二活动区域中的凹陷的升高的S / D区域上。 第一和第二自对准触点允许独立地减少源漏接触电阻。 第一自对准触点可以是MIS触点或金属硅化物触点，并且第二自对准触点可以是金属硅化物触点。

公开(公告)号：US20170040226A1

公开(公告)日：2017-02-09

申请号：US15299216

申请日：2016-10-20

申请人： Renesas Electronics Corporation

发明人： Hidekazu ODA

IPC分类号： H01L21/84 ,  H01L21/265 ,  H01L27/12 ,  H01L21/822 ,  H01L29/66

CPC分类号： H01L29/6656 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.

摘要翻译： 为了提高具有完全耗尽的SOI晶体管的半导体器件的可靠性和性能，而形成在栅电极的侧壁上的偏移间隔物的宽度被配置为大于或等于半导体层的厚度并且更小 除了半导体层的厚度和绝缘膜的厚度的总和的厚度以外，杂质被离子注入到未被栅电极和偏移间隔物覆盖的半导体层中。 因此，通过离子注入杂质形成的延伸层不会从低于栅电极的端部的位置进入沟道。

公开(公告)号：US20160365422A1

公开(公告)日：2016-12-15

申请号：US15246262

申请日：2016-08-24

申请人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/06

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28105 ,  H01L21/823443 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

摘要翻译： 具有反掺杂导电栅极的集成电路器件。 这些器件具有具有衬底表面的半导体衬底。 器件还具有第一导电类型的第一阱，第二导电类型的源极和第二导电类型的漏极。 通道在源极和漏极之间延伸。 导电栅极延伸穿过沟道。导电栅极包括第一导电类型的第一栅极区域和第二栅极区域以及第一导电类型的第三栅极区域。 第三栅极区域在第一和第二栅极区域之间延伸。 器件还包括在导电栅极和衬底之间延伸并且还包括与第一，第二和第三栅极区域电连通的硅化物区域的栅极电介质。 这些方法包括制造器件的方法。

公开(公告)号：US09520495B2

公开(公告)日：2016-12-13

申请号：US14863362

申请日：2015-09-23

申请人： SK hynix Inc.

发明人： Yun-Hyuck Ji

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/324 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7845 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66515 ,  H01L29/66575 ,  H01L29/78

摘要： A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel.