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23 条记录 (耗时 0.178 秒)

    Self-aligned source/drain contacts
    1.
    发明授权
    Self-aligned source/drain contacts 有权

    公开(公告)号：US10121789B2

    公开(公告)日：2018-11-06

    申请号：US15396924

    申请日：2017-01-03

    申请人： International Business Machines Corporation

    发明人： Praneet Adusumilli ,  Emre Alptekin ,  Kangguo Cheng ,  Balasubramanian Pranatharthiharan ,  Shom S. Ponoth

    IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417

    摘要： A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

    Bi-layer gate cap for self-aligned contact formation
    5.
    发明授权
    Bi-layer gate cap for self-aligned contact formation 有权
    用于自对准接触形成的双层栅极盖

    公开(公告)号：US09064801B1

    公开(公告)日：2015-06-23

    申请号：US14161721

    申请日：2014-01-23

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Samsung Electronics Co., Ltd.

    发明人： David V. Horak ,  Jin Wook Lee ,  Daniel Pham ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan

    IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L21/283

    CPC分类号： H01L21/283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    摘要： A method of forming a semiconductor structure includes forming a metal gate above a semiconductor substrate and gate spacers adjacent to the metal gate surrounded by an interlevel dielectric (ILD) layer. The gate spacers and the metal gate are recessed until a height of the metal gate is less than a height of the gate spacers. An etch stop liner is deposited above the gate spacers and the metal gate. A gate cap is deposited above the etch stop liner to form a bi-layer gate cap. A contact hole is formed in the ILD layer adjacent to the metal gate, the etch stop liner in the bi-layer gate cap prevents damage of the gate spacers during formation of the contact hole. A conductive material is deposited in the contact hole to form a contact to a source-drain region in the semiconductor substrate.

    摘要翻译： 形成半导体结构的方法包括在半导体衬底之上形成金属栅极和邻近由层间电介质（ILD）层围绕的金属栅极的栅极间隔。 栅极间隔物和金属栅极凹入直到金属栅极的高度小于栅极间隔物的高度。 蚀刻停止衬垫沉积在栅极间隔物和金属栅极上方。 栅极盖沉积在蚀刻停止衬垫上方以形成双层栅极盖。 在与金属栅极相邻的ILD层中形成接触孔，双层栅极帽中的蚀刻停止衬垫防止在形成接触孔期间损坏栅极间隔物。 导电材料沉积在接触孔中以与半导体衬底中的源极 - 漏极区形成接触。

    FIN CAPACITOR EMPLOYING SIDEWALL IMAGE TRANSFER
    6.
    发明申请
    FIN CAPACITOR EMPLOYING SIDEWALL IMAGE TRANSFER 有权
    FIN电容器采用小尺寸图像传输

    公开(公告)号：US20150145008A1

    公开(公告)日：2015-05-28

    申请号：US14088473

    申请日：2013-11-25

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Shom S. Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L49/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/538

    CPC分类号： H01L21/823431 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/0629 ,  H01L28/90 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Spacer structures are formed around an array of disposable mandrel structures and above a doped semiconductor material portion. A sidewall image transfer process is employed to pattern an upper portion of the doped semiconductor material portion into an array of doped semiconductor fins. After formation of a dielectric material layer on the top surfaces and sidewall surfaces of the doped semiconductor fins, gate-level mandrel structures are formed to straddle multiple semiconductor fins. A conductive hole-containing structure is formed to laterally surround a plurality of gate-level mandrel structures, which is subsequently removed. A contact-level dielectric layer is formed over the conductive hole-containing structure and the plurality of doped semiconductor fins. The semiconductor fins function as a lower electrode of a fin capacitor, and the conductive hole-containing structure functions as an upper electrode of the fin capacitor.

    摘要翻译： 间隔结构形成在一次性心轴结构的阵列周围并且在掺杂的半导体材料部分之上。 采用侧壁图像转移处理将掺杂半导体材料部分的上部图案化成掺杂半导体鳍片的阵列。 在掺杂半导体鳍片的顶表面和侧壁表面上形成介电材料层之后，形成跨越多个半导体鳍片的门级芯棒结构。 形成导电孔结构以横向围绕多个门级芯棒结构，随后将其移除。 在含导电孔的结构和多个掺杂的半导体鳍片之上形成接触电介质层。 半导体鳍片用作散热片电容器的下电极，并且导电孔结构用作散热片电容器的上电极。

    REDUCED EXTERNAL RESISTANCE FINFET DEVICE
    7.
    发明申请
    REDUCED EXTERNAL RESISTANCE FINFET DEVICE 有权
    减少外部电阻FINFET器件

    公开(公告)号：US20160196973A1

    公开(公告)日：2016-07-07

    申请号：US14591041

    申请日：2015-01-07

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Shom S. Ponoth ,  Raghavasimhan Sreenivasan ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/02 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/785 ,  H01L29/161 ,  H01L29/66553 ,  H01L29/66795

    摘要： The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin field effect transistor (finFET) devices. A first spacer and a second spacer may be formed adjacent to a gate which may reduce capacitance in a substantial portion of a epitaxial source-drain region while also permitting a portion of the epitaxial source-drain region to be located close to a channel. By reducing capacitance from the gate on the substantial portion of the epitaxial source-drain region, resistance in the epitaxial source-drain region may be reduced which may result in increased device performance.

    摘要翻译： 本发明一般涉及半导体器件，更具体地说，涉及一种降低鳍式场效应晶体管（finFET）器件内的外部电阻的结构和方法。 第一间隔物和第二间隔物可以与栅极相邻地形成，这可以减小外延源极 - 漏极区域的大部分中的电容，同时还允许外延源极 - 漏极区域的一部分位于靠近沟道的位置。 通过减小来自外延源极 - 漏极区域的基本部分上的栅极的电容，外延源极 - 漏极区域中的电阻可能降低，这可能导致器件性能的提高。

    Fin capacitor employing sidewall image transfer
    8.
    发明授权
    Fin capacitor employing sidewall image transfer 有权
    Fin电容采用侧壁图像传输

    公开(公告)号：US09224654B2

    公开(公告)日：2015-12-29

    申请号：US14088473

    申请日：2013-11-25

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Shom S. Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L27/108 ,  H01L21/8234 ,  H01L23/538 ,  H01L27/06 ,  H01L49/02

    CPC分类号： H01L21/823431 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/0629 ,  H01L28/90 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Spacer structures are formed around an array of disposable mandrel structures and above a doped semiconductor material portion. A sidewall image transfer process is employed to pattern an upper portion of the doped semiconductor material portion into an array of doped semiconductor fins. After formation of a dielectric material layer on the top surfaces and sidewall surfaces of the doped semiconductor fins, gate-level mandrel structures are formed to straddle multiple semiconductor fins. A conductive hole-containing structure is formed to laterally surround a plurality of gate-level mandrel structures, which is subsequently removed. A contact-level dielectric layer is formed over the conductive hole-containing structure and the plurality of doped semiconductor fins. The semiconductor fins function as a lower electrode of a fin capacitor, and the conductive hole-containing structure functions as an upper electrode of the fin capacitor.

    摘要翻译： 间隔结构形成在一次性心轴结构的阵列周围并且在掺杂的半导体材料部分之上。 采用侧壁图像转移处理将掺杂半导体材料部分的上部图案化成掺杂半导体鳍片的阵列。 在掺杂半导体鳍片的顶表面和侧壁表面上形成介电材料层之后，形成跨越多个半导体鳍片的门级芯棒结构。 形成导电孔结构以横向围绕多个门级芯棒结构，随后将其移除。 在含导电孔的结构和多个掺杂的半导体鳍片之上形成接触电介质层。 半导体鳍片用作散热片电容器的下电极，并且导电孔结构用作散热片电容器的上电极。

    Spacer replacement for replacement metal gate semiconductor devices
    9.
    发明授权
    Spacer replacement for replacement metal gate semiconductor devices 有权
    替代金属栅极半导体器件的间隔件替代

    公开(公告)号：US09171927B2

    公开(公告)日：2015-10-27

    申请号：US13850470

    申请日：2013-03-26

    申请人： International Business Machines Corporation

    发明人： Sanjay C. Mehta ,  Shom S. Ponoth ,  Muthumanickam Sankarapandian ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/336 ,  H01L21/311 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/66553 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785

    摘要： A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.

    摘要翻译： 一种方法，包括从具有牺牲栅极的半导体器件去除包括硬掩模层和一个或多个间隔物材料层的第一介电材料的步骤，所述牺牲栅极的侧壁被所述间隔物材料层覆盖，以及升高的源极和升高的漏极 其中所述牺牲栅极与所述牺牲栅极一起被所述硬掩模层覆盖，其中所述去除对所述牺牲栅极，升高的源极区域和升高的漏极区域是选择性的，并且在每个所述升高的源极区域，升高的漏极区域 和牺牲门。 该方法包括将第二介电材料的共形层沉积到半导体器件中，其中第二材料在均匀的层中符合升高的源极区域，升高的漏极区域和牺牲栅极，并且填充每个凸起源极区域之间的空隙 ，凸起的漏极区域和牺牲栅极。

    FORMING ISOLATED FINS FROM A SUBSTRATE
    10.
    发明申请
    FORMING ISOLATED FINS FROM A SUBSTRATE 有权
    从基底形成分离的FINS

    公开(公告)号：US20150102409A1

    公开(公告)日：2015-04-16

    申请号：US14050661

    申请日：2013-10-10

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/845 ,  H01L21/32 ,  H01L21/76243 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795

    摘要： A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a top portion of the fin above the masking layer, removing the masking layer to expose the base portion of the fin, and converting the base portion of the fin to an isolation region that electrically isolates the fin from the substrate. The base portion of the fin may be converted to an isolation region by oxidizing the base portion of the fin, using for example a thermal oxidation process. While converting the base portion of the fin to an isolation region, the spacers prevent the top portion of the fin from also being converted.

    摘要翻译： 一种从下面的衬底隔离半导体鳍片的方法，包括在鳍片的基底部分周围形成掩模层，在掩模层上方的翅片的顶部上形成间隔物，去除掩模层以暴露鳍片的基底部分 ，并且将鳍的基部转换成将鳍与基板电隔离的隔离区。 通过使用例如热氧化工艺，可以通过氧化散热片的基部来将散热片的基部转换成隔离区。 在将翅片的基部转换成隔离区域的同时，间隔物防止鳍的顶部也被转换。