公开(公告)号：US11665900B2

公开(公告)日：2023-05-30

申请号：US16853416

申请日：2020-04-20

Applicant: SAMSUNG ELCTRONICS CO., LTD.

Inventor： Younghwan Son ,  Juyoung Lim ,  Sunil Shim ,  Suhyeong Lee ,  Sanghoon Jeong

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A vertical memory device includes a channel extending vertically on a substrate. A charge storage structure is disposed on a sidewall of the channel. Gate electrodes are spaced apart from each other vertically and surround the charge storage structure. A first insulation pattern includes an air gap between the gate electrodes. The charge storage structure includes a tunnel insulation layer, a charge trapping pattern, and a first blocking pattern sequentially stacked horizontally. The charge storage structure includes charge trapping patterns spaced apart from each other vertically. Each of the charge trapping patterns faces one of the gate electrodes horizontally. A length in the first direction of an outer sidewall of each of the charge trapping patterns facing the first blocking pattern is less than that of an inner sidewall thereof facing the tunnel insulation layer.

公开(公告)号：US11664281B2

公开(公告)日：2023-05-30

申请号：US17570990

申请日：2022-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui Chang Moon

IPC: H01L27/1157 ,  H01L29/10 ,  H01L29/792 ,  H01L29/167 ,  H01L29/66 ,  H01L27/11582 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823487 ,  H01L21/02172 ,  H01L21/76224 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure disposed on a lower structure; an insulating structure disposed on the stack structure; and a vertical structure extending in a direction perpendicular to an upper surface of the lower structure and having side surfaces opposing the stack structure and the insulating structure. The stack structure includes interlayer insulating layers and gate layers, alternately stacked, and the insulating structure includes a lower insulating layer, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer.

公开(公告)号：US20230165000A1

公开(公告)日：2023-05-25

申请号：US17970764

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Seok CHOI ,  Kyoung Sun KIM ,  Hee Jeong SON ,  Min Ju KANG ,  Seong Joon AHN

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C5/06

Abstract: A semiconductor memory device includes a cell substrate including a cell array region and an extended region, gate electrodes stacked on the cell substrate, the gate electrodes including molybdenum, and channel structures in the cell array region, the channel structures penetrating the gate electrodes, wherein at least one of the gate electrodes includes at least one void in a region between the channel structures.

公开(公告)号：US11657875B2

公开(公告)日：2023-05-23

申请号：US17849062

申请日：2022-06-24

Applicant: KIOXIA CORPORATION

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Riki Suzuki ,  Masanobu Shirakawa ,  Toshikatsu Hida

IPC: G06F12/00 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C16/32 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3459 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C11/5671 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

公开(公告)号：US20190252407A1

公开(公告)日：2019-08-15

申请号：US16391479

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: H01L27/11597 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/1159 ,  H01L29/78 ,  H01L29/423 ,  H01L27/11587

CPC classification number: H01L27/11597 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/78391

Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

公开(公告)号：US20190252406A1

公开(公告)日：2019-08-15

申请号：US16394867

申请日：2019-04-25

Applicant: SK hynix Inc.

Inventor： Nam Jae LEE

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/768 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device includes a first channel layer and a second channel layer, each extending from an upper portion to a lower portion; and word lines stacked toward the upper portion from the lower portion, the word lines spaced apart from each other, the word lines each extending to surround the first channel layer and the second layer; a first lower select group surrounding a portion of the first channel layer that further protrudes toward the lower portion than the word lines; and a second lower select group surrounding a portion of the second channel layer that further protrudes toward the lower portion than the word lines.

公开(公告)号：US20190252394A1

公开(公告)日：2019-08-15

申请号：US16396963

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US20190252021A1

公开(公告)日：2019-08-15

申请号：US16391041

申请日：2019-04-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi MAEJIMA

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  G11C7/06 ,  H01L23/528 ,  G11C16/08 ,  G11C16/26 ,  G11C5/06 ,  H01L23/522

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C7/06 ,  G11C16/08 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

公开(公告)号：US20190244971A1

公开(公告)日：2019-08-08

申请号：US16252301

申请日：2019-01-18

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/528 ,  H01L29/786 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/30 ,  G11C16/14 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/04 ,  G11C16/26

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/78642

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

公开(公告)号：US20190244970A1

公开(公告)日：2019-08-08

申请号：US16139775

申请日：2018-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  JoongShik SHIN ,  SangJun HONG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.