公开(公告)号：US20160013093A1

公开(公告)日：2016-01-14

申请号：US14864080

申请日：2015-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L29/0649 ,  H01L21/02065 ,  H01L21/02181 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32055 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5227 ,  H01L23/5256 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/08 ,  H01L27/1203 ,  H01L28/10 ,  H01L28/20 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

公开(公告)号：US20150372112A1

公开(公告)日：2015-12-24

申请号：US14307575

申请日：2014-06-18

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02107 ,  H01L21/28132 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.

公开(公告)号：US20150372109A1

公开(公告)日：2015-12-24

申请号：US14519615

申请日：2014-10-21

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/3205 ,  H01L29/51 ,  H01L21/02 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/02107 ,  H01L21/28132 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed.

Abstract translation: 在形成跨越至少一个半导体材料部分的栅极腔形成之后，在栅极介电层上形成栅极电介质层和至少一个功函数材料层。 图案化至少一个功函数材料层和栅介电层，使得至少一个功函数材料层的剩余部分仅存在于至少一个半导体材料部分附近。 具有比至少一个功函数材料层更大的导电性的导电材料沉积在栅极腔的剩余部分中。 替代栅极结构中的导电材料部分在去除至少一个功函数材料层和栅极介电层的区域中具有替换栅极结构的全宽。

公开(公告)号：US09219059B2

公开(公告)日：2015-12-22

申请号：US13627162

申请日：2012-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L21/822 ,  H01L27/06 ,  H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L21/762 ,  H01L21/763

CPC classification number: H01L29/0649 ,  H01L21/02065 ,  H01L21/02181 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32055 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5227 ,  H01L23/5256 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/08 ,  H01L27/1203 ,  H01L28/10 ,  H01L28/20 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

Abstract translation: 公开了具有集成的被动结构的金属氧化物半导体场效应晶体管（MOSFET）及其制造方法。 该方法包括在有源区域中形成层叠结构，以及在层叠结构附近形成至少一个浅沟槽隔离（STI）结构。 该方法还包括形成直接与至少一个STI结构和堆叠结构接触的半导体层。 该方法还包括图案化半导体层和层叠结构，以在有源区域中形成有源器件，并且在至少一个STI结构上直接形成半导体层的无源结构。

公开(公告)号：US20150270284A1

公开(公告)日：2015-09-24

申请号：US14217572

申请日：2014-03-18

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Murshed M. Chowdhury ,  Arvind Kumar ,  Robert R. Robison

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/167 ,  H01L21/225 ,  H01L21/265 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L27/1203 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L21/84 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.

Abstract translation: 在绝缘体上半导体（SOI）衬底的顶部半导体层中形成源极/漏极沟槽之后，半导体结构的相邻沟道区的沟槽的部分被形成在沟槽的侧壁上的牺牲隔离物或由光刻胶层 部分。 牺牲间隔物或光致抗蚀剂层部分屏蔽沟槽下方的顶部半导体层的部分以及后续的离子注入以形成结对接。 因此，离子注入区仅限于远离半导体结构的沟道区的顶部半导体层的未屏蔽的亚层部分。 控制离子注入区域的宽度，使得注入的掺杂剂在随后的热循环期间不扩散到沟道区域中，以便抑制短沟道效应。

公开(公告)号：US20140312404A1

公开(公告)日：2014-10-23

申请号：US13865267

申请日：2013-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar

IPC: H01L27/12 ,  H01L27/105

CPC classification number: H01L27/1203 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/7883

Abstract: A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.

Abstract translation: 提供用于集成SOI CMOS FET和NVRAM存储器件的结构和方法。 该结构包括含有半导体衬底，SOI层和形成在半导体衬底和SOI层之间的BOX层的SOI衬底。 SOI衬底包括预定义的SOI器件和NVRAM器件区域。 在SOI器件区域中形成SOI FET。 SOI FET包括BOX层和SOI层的部分，SOI FET栅极电介质层和栅极导体层。 该结构还包括形成在NVRAM器件区域中的NVRAM器件。 NVRAM器件包括隧道氧化物，浮动栅极，阻塞氧化物和控制栅极层。 隧道氧化物层与SOI器件区域中BOX层的部分共面。 浮置栅极层与SOI器件区域中的半导体层的部分共面。

公开(公告)号：US20140206160A1

公开(公告)日：2014-07-24

申请号：US14220437

申请日：2014-03-20

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Edward P. Maciejewski ,  Shreesh Narasimha ,  Dustin K. Slisher

IPC: H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/8238 ,  H01L21/265 ,  H01L21/77 ,  H01L21/823835 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/861

Abstract: A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

Abstract translation: 一种制造半导体结构的方法，该半导体结构设置有具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的多个门控二极管和由非硅化栅极材料制成的高K栅极堆叠 与FET相邻的二极管，其每一个具有硅化源，硅化物漏极和硅化HiK栅极堆叠。 半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。 优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。 没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

公开(公告)号：US20240363617A1

公开(公告)日：2024-10-31

申请号：US18306487

申请日：2023-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence Hook ,  Brent A. Anderson ,  Ruilong Xie ,  Anthony I. Chou ,  John Christopher Arnold ,  Nicholas Alexander POLOMOFF

IPC: H01L27/02 ,  H01L21/84 ,  H02H9/04

CPC classification number: H01L27/0255 ,  H01L21/84 ,  H01L27/0292 ,  H02H9/046

Abstract: An ESD protection device is disclosed that uses a BSPDN to provide potential(s) to the ESD protection device. The utilization of the BSPDN reduces resistance drops induced during high current ESD events, which results in robust ESD protection. The utilization of the BSPDN also reduces the footprint area of the ESD protection circuit relative to known ESD protection devices that utilize respective frontside contacts to VDD, VSS, and I/O. Further, the disclosed ESD protection circuit may utilize the same or similar structures as that are used by microdevices (e.g., transistors, or the like) within the semiconductor IC device, which may decrease fabrication complexities thereof.

公开(公告)号：US20240290860A1

公开(公告)日：2024-08-29

申请号：US18113686

申请日：2023-02-24

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Nicolas Jean Loubet ,  Andrew M. Greene ,  Andrew Gaul ,  Ruilong Xie ,  Shogo Mochizuki ,  Curtis S. Durfee ,  Eric Miller ,  Ronald Newhart ,  Choudhury Mahboob Ellahi ,  Anthony I. Chou ,  Susan Ng Emans

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor structure includes a substrate and a gate-all-around field effect transistor disposed over the substrate. The gate-all-around field effect transistor includes a first source-drain region; a second source-drain region; at least one channel region interconnecting the first and second source drain regions; and a gate structure surrounding the at least one channel region. A self-aligned substrate isolation (SASI) layer is located between the substrate and the gate structure and extends over a width of the gate structure.

公开(公告)号：US20230411241A1

公开(公告)日：2023-12-21

申请号：US17841202

申请日：2022-06-15

Applicant: International Business Machines Corporation

Inventor： Terence Hook ,  Brent A. Anderson ,  Anthony I. Chou

IPC: H01L23/427 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L23/427 ,  H01L27/1203 ,  H01L23/5226

Abstract: A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs. The heat pipe includes at least one vertical interconnect structure that continuously extends between each tier of the vertically stacked FETs