公开(公告)号：US20170133461A1

公开(公告)日：2017-05-11

申请号：US15409065

申请日：2017-01-18

申请人： Intel Corporation

发明人： Walid M. HAFEZ ,  Chia-Hong JAN

IPC分类号： H01L29/06 ,  H01L27/098

CPC分类号： H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

摘要： A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US09536789B1

公开(公告)日：2017-01-03

申请号：US15007616

申请日：2016-01-27

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Tak H. Ning

IPC分类号： H01L27/088 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/66 ,  H01L29/40 ,  H01L29/16

CPC分类号： H01L27/0886 ,  H01L21/3065 ,  H01L21/8232 ,  H01L27/085 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/66916 ,  H01L29/808

摘要： A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

摘要翻译： 提供了在共同的基板上形成双门控结型场效应晶体管（JFET）和三栅极金属氧化物半导体场效应晶体管（MOSFET）的方法。 双门控JFET通过形成半导体栅极电极而形成在衬底的第一区域中，半导体栅电极接触第一半导体鳍片的第一沟道区域的侧壁表面和在第一沟道区域顶部的第一鳍片帽部分的顶表面 。 三栅极MOSFET通过形成接触第二半导体鳍片的第二沟道区域的顶表面和侧壁表面的金属栅叠层形成在衬底的第二区域中。

公开(公告)号：US20160293602A1

公开(公告)日：2016-10-06

申请号：US14677404

申请日：2015-04-02

申请人： STMicroelectronics, Inc.

发明人： Qing Liu ,  John Hongguang Zhang

IPC分类号： H01L27/098 ,  H01L29/808 ,  H01L21/283 ,  H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

摘要： A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

摘要翻译： 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。

公开(公告)号：US09293465B1

公开(公告)日：2016-03-22

申请号：US14483851

申请日：2014-09-11

申请人： John V. Veliadis

发明人： John V. Veliadis

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/098 ,  H01L21/8232 ,  H01L29/808 ,  H01L29/06

CPC分类号： H01L27/088 ,  G06F8/33 ,  G06F8/72 ,  G06F8/75 ,  H01L21/8232 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

摘要： A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.

摘要翻译： 单片双向器件提供双向功率流和双向阻断高电压。 该器件包括第一晶体管，其具有形成在覆盖衬底的第一沟道层上的第一漏极，以及第二晶体管，其包括形成在覆盖衬底的第二沟道层上的第二漏极。 衬底形成用于第一晶体管和第二晶体管的公共源极。

公开(公告)号：US20160079244A1

公开(公告)日：2016-03-17

申请号：US14483851

申请日：2014-09-11

申请人： JOHN V. VELIADIS

发明人： JOHN V. VELIADIS

IPC分类号： H01L27/098 ,  H01L29/808 ,  H01L29/06 ,  H01L21/8232

CPC分类号： H01L27/088 ,  G06F8/33 ,  G06F8/72 ,  G06F8/75 ,  H01L21/8232 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

摘要： A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.

公开(公告)号：US09287413B2

公开(公告)日：2016-03-15

申请号：US13892960

申请日：2013-05-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Chung Chen ,  Chi-Feng Huang

IPC分类号： H01L29/808 ,  H01L21/337 ,  H01L29/772 ,  H01L21/336 ,  H01L27/085 ,  H01L27/07 ,  H01L21/8249 ,  H01L29/76 ,  H01L29/66 ,  H01L29/06 ,  H01L27/098 ,  H01L21/762 ,  H01L29/423

CPC分类号： H01L29/808 ,  H01L21/762 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/66901

摘要： A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region is configured to cause a depletion region in one of the source and drain regions.

摘要翻译： 结栅场效应晶体管（JFET）包括衬底，形成在衬底中的源极区，形成在衬底中的漏极区，形成在衬底中的沟道区，以及形成在衬底中的至少一个栅极区。 沟道区域连接源区和漏区。 至少一个栅极区域被配置为在源极区域和漏极区域之一引起耗尽区域。

公开(公告)号：US08928410B2

公开(公告)日：2015-01-06

申请号：US13803792

申请日：2013-03-14

申请人： ACCO Semiconductor, Inc.

发明人： Alexandre G. Bracale ,  Denis A. Masliah

IPC分类号： H03F3/16 ,  H01L27/088 ,  H01L21/82 ,  H01L27/06 ,  H03F1/22 ,  H03F3/195 ,  H03F3/24 ,  H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H01L27/095 ,  H01L27/098

CPC分类号： H01L27/088 ,  H01L21/82 ,  H01L27/0617 ,  H01L27/095 ,  H01L27/098 ,  H03F1/0266 ,  H03F1/223 ,  H03F1/56 ,  H03F3/1935 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/387

摘要： Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

摘要翻译： 提供电子电路和方法用于各种应用，包括信号放大。 示例性电子电路包括MOSFET和共栅二极管配置的双栅极JFET。 双栅极JFET包括设置在通道上方和下方的顶部和底部门。 JFET的顶栅由信号控制，该信号取决于控制MOSFET栅极的信号。 JFET的底栅的控制可以取决于或不依赖于顶栅的控制。 MOSFET和JFET可以在不同尺寸（如栅极宽度）的同一衬底上实现为单独的组件。

公开(公告)号：US08835934B2

公开(公告)日：2014-09-16

申请号：US13414394

申请日：2012-03-07

申请人： Makoto Mizukami

发明人： Makoto Mizukami

IPC分类号： H01L29/78 ,  H01L29/47 ,  H01L29/161 ,  H01L29/16 ,  H01L27/098 ,  H01L27/07 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06

CPC分类号： H01L27/0727 ,  H01L27/098 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/7806

摘要： A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.

摘要翻译： 半导体器件包括第一导电型半导体衬底，第一导电型半导体淀积层，沟槽，第二导电型阱，JFET区，第一导电型第一源极区，第一源极区，沟槽型源电极 栅极绝缘膜，栅电极和漏电极。 沟槽基本上垂直于半导体淀积层形成，使得半导体沉积层暴露于沟槽的底部。 第二导电类型的第二源极区域形成在第一导电型第一源极区域中。 沟槽型源电极与第一源极区域，第二源极区域和第一导电型半导体沉积层接触以构成肖特基结。

公开(公告)号：US08455948B2

公开(公告)日：2013-06-04

申请号：US12986784

申请日：2011-01-07

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H01L29/161 ,  H01L27/088 ,  H01L27/098 ,  H01L29/20

CPC分类号： H01L27/0883 ,  H01L21/823418 ,  H01L21/823437 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838

摘要： A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.

摘要翻译： 晶体管装置包括具有漂移区和多个第二晶体管的第一晶体管，每个具有源极区，漏极区和栅电极。 第二晶体管串联耦合以形成与第一晶体管的漂移区域并联耦合的串联电路。

公开(公告)号：US20130056801A1

公开(公告)日：2013-03-07

申请号：US13659386

申请日：2012-10-24

申请人： PANASONIC CORPORATION

发明人： Tomohiro MATSUNAGA ,  Tsuneichiro SANO

IPC分类号： H01L29/808 ,  H01L27/098

CPC分类号： H01L29/808 ,  H01L29/0696 ,  H01L29/66901 ,  H03F3/1935 ,  H03F3/45381 ,  H03F3/50

摘要： A junction field effect transistor comprising: a semiconductor substrate having a first conductivity type; a channel region having a second conductivity type different from the first conductivity type, and being formed in a surface of the semiconductor substrate; a first buried region having the second conductivity type, being formed within the channel region, and having an impurity concentration higher than the channel region; a first gate region having the first conductivity type, and being formed in a surface of the channel region; and first drain/source region and a second drain/source region both having the second conductivity type, which are formed each on an opposite side of the first gate region in the surface of the channel region, in which the first buried region is not formed below the second drain/source region, but is formed below the first drain/source region.

摘要翻译： 一种结型场效应晶体管，包括：具有第一导电类型的半导体衬底; 具有不同于第一导电类型的第二导电类型的沟道区，并形成在半导体衬底的表面中; 具有第二导电类型的第一掩埋区，形成在沟道区内，杂质浓度高于沟道区; 具有第一导电类型的第一栅极区，并形成在沟道区的表面中; 以及第一漏极/源极区域和第二漏极/源极区域，其具有第二导电类型，其在沟道区域的表面中的第一栅极区域的相对侧上形成，其中不形成第一掩埋区域 但是形成在第一漏极/源极区域的下方。