公开(公告)号：US09105533B2

公开(公告)日：2015-08-11

申请号：US14507189

申请日：2014-10-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A bump structure includes a first end, and a second end opposite the first end. The bump structure further includes a first side connected between the first end and the second end. The bump structure further includes a second side opposite the first side. The second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill.

Abstract translation: 凸块结构包括第一端和与第一端相对的第二端。 凸起结构还包括连接在第一端和第二端之间的第一侧。 凸起结构还包括与第一侧相对的第二侧。 第二侧连接在第一端和第二端之间，第二侧包括用于填充回流焊料的凹部。

公开(公告)号：US08803338B2

公开(公告)日：2014-08-12

申请号：US14057045

申请日：2013-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Chih-Horng Chang

IPC: H01L23/02

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/535 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03848 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2924/01046 ,  H01L2924/01039 ,  H01L2924/01016 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2224/034 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a copper-containing metallization layer, a nickel-containing metallization layer, and a first intermetallic compound (IMC) layer between the copper-containing metallization layer and the nickel-containing metallization layer. The first IMC layer is in direct contact with the copper-containing metallization layer and the nickel-containing metallization layer.

Abstract translation: 半导体器件包括半导体衬底，覆盖半导体衬底的凸起下金属化（UBM）结构以及覆盖并电连接到UBM结构的焊料凸块。 UBM结构包括含铜金属化层，含镍金属化层和位于含铜金属化层和含镍金属化层之间的第一金属间化合物（IMC）层。 第一IMC层与含铜金属化层和含镍金属化层直接接触。

公开(公告)号：US20240371814A1

公开(公告)日：2024-11-07

申请号：US18776271

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chia Lai ,  Chih-Horng Chang ,  Hao-Yi Tsai ,  Chih-Hsuan Tai

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a redistribution circuit structure. The semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure includes conductive patterns, wherein the conductive patterns each comprise a first portion, at least one second portion, and at least one connecting portion. A first edge of the at least one connecting portion is connected to the first portion, and a second edge of the at least one connecting portion is connected to the at least one second portion, wherein the first edge is opposite to the second edge, and a length of the first edge is greater than a length of the second edge.

公开(公告)号：US12087718B2

公开(公告)日：2024-09-10

申请号：US18300493

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16056 ,  H01L2224/16059 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/384 ,  Y10T428/12493 ,  Y10T428/24479

Abstract: The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.

公开(公告)号：US20230253355A1

公开(公告)日：2023-08-10

申请号：US18300493

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/13 ,  H01L24/14 ,  H01L24/11 ,  H01L25/50 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/2064 ,  H01L2924/384 ,  H01L2224/13012 ,  H01L2224/05552 ,  H01L2224/81345 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2924/01322 ,  Y10T428/24479 ,  Y10T428/12493 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2224/81191 ,  H01L2224/16238 ,  H01L2224/13147 ,  H01L2224/131 ,  H01L2224/13083 ,  H01L2224/13082 ,  H01L2224/05599 ,  H01L2224/0401 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/14051 ,  H01L2224/10145 ,  H01L2224/1412

Abstract: The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.

公开(公告)号：US11049805B2

公开(公告)日：2021-06-29

申请号：US16266446

申请日：2019-02-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo Lung Pan ,  Shu-Rong Chun ,  Teng-Yuan Lo ,  Hung-Yi Kuo ,  Chih-Horng Chang ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

公开(公告)号：US20200126893A1

公开(公告)日：2020-04-23

申请号：US16717136

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Jie-Cheng Deng ,  Tin-Hao Kuo ,  Ying-Yu Chen

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

公开(公告)号：US10522444B2

公开(公告)日：2019-12-31

申请号：US13895099

申请日：2013-05-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Jie-Cheng Deng ,  Tin-Hao Kuo ,  Ying-Yu Chen

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

公开(公告)号：US09048333B2

公开(公告)日：2015-06-02

申请号：US14189584

申请日：2014-02-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Tsung-Fu Tsai ,  Min-Feng Ku

IPC: H01L21/00 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3121 ,  H01L21/304 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00

Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.

Abstract translation: 一种装置包括第一包装部件和第二包装部件，所述第一包装部件和第二包装部件下面并结合到第一包装部件。 成型材料设置在第一包装部件下方并被模制到第一和第二包装部件上，其中成型材料和第一包装部件形成界面。 隔离区域包括第一边缘，其中隔离区域的第一边缘接触第一封装部件的第一边缘和模制材料的第一边缘。 隔离层的底部低于界面。

公开(公告)号：US20150104903A1

公开(公告)日：2015-04-16

申请号：US14550337

申请日：2014-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/11823 ,  H01L2224/11824 ,  H01L2224/11831 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0541 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/00

Abstract: A die has a top surface, and a metal pillar having a portion protruding over the top surface of the die. A sidewall of the metal pillar has nano-wires. The die is bonded to a package substrate. An underfill is filled into the gap between the die and the package substrate.

Abstract translation: 模具具有顶表面和金属柱，其具有在模具的顶表面上突出的部分。 金属柱的侧壁具有纳米线。 模具结合到封装衬底。 将底部填充物填充到管芯和封装衬底之间的间隙中。