公开(公告)号：US09240331B2

公开(公告)日：2016-01-19

申请号：US14039418

申请日：2013-09-27

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  See Chian Lim ,  HeeJo Chi

IPC: H01L23/52 ,  H01L29/40 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4867 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/10165 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13316 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13794 ,  H01L2224/138 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1701 ,  H01L2224/17517 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/8114 ,  H01L2224/81192 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.

Abstract translation: 半导体器件包括具有接触焊盘的衬底。 掩模设置在基板上。 铝可润湿的导电浆料印刷在基材的接触垫上。 将半导体管芯设置在铝可润湿的导电膏上。 铝可湿性导电膏被回流以在衬底的接触焊盘上形成互连结构。 接触垫包括铝。 半导体管芯的接触焊盘设置在铝可润湿的导电膏上。 铝可润湿的导电膏被回流以在半导体管芯的接触焊盘和衬底的接触焊盘之间形成互连结构。 互连结构直接形成在基板和半导体管芯的接触焊盘上。 在回流铝可湿性导电膏之前，蚀刻半导体管芯的接触焊盘。 环氧预处理点，以保持半导体管芯和衬底之间的间隔。

公开(公告)号：US20150171024A1

公开(公告)日：2015-06-18

申请号：US14109313

申请日：2013-12-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate including a base substrate material and a plurality of conductive vias formed partially though the substrate. A plurality of semiconductor die including a base semiconductor material is disposed over the substrate. A ratio of an encapsulant to a quantity of the semiconductor die is determined for providing structural support for the semiconductor die. An encapsulant is deposited over the semiconductor die and substrate. An amount of the encapsulant is selected based on the determined ratio or based on a total amount of the base substrate material and base semiconductor material. Channels are formed in the encapsulant by removing a portion of the encapsulant in a peripheral region of the semiconductor die. Alternatively, a side surface of the semiconductor die is partially exposed with respect to the encapsulant. A portion of the base substrate material is removed to expose the conductive vias.

Abstract translation: 半导体器件具有包括基底材料和部分地通过衬底形成的多个导电通孔的衬底。 包括基底半导体材料的多个半导体管芯设置在基板上。 确定密封剂与半导体管芯的量的比率以提供半导体管芯的结构支撑。 密封剂沉积在半导体管芯和衬底上。 基于确定的比例或基于基底材料和基底半导体材料的总量来选择一定量的密封剂。 通过在半导体管芯的周边区域中去除一部分密封剂而在密封剂中形成通道。 或者，半导体管芯的侧表面相对于密封剂部分地露出。 去除基底衬底材料的一部分以露出导电通孔。

公开(公告)号：US20140175661A1

公开(公告)日：2014-06-26

申请号：US14039418

申请日：2013-09-27

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  See Chian Lim ,  HeeJo Chi

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/4867 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/10165 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13316 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13794 ,  H01L2224/138 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1701 ,  H01L2224/17517 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/8114 ,  H01L2224/81192 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.

Abstract translation: 半导体器件包括具有接触焊盘的衬底。 掩模设置在基板上。 铝可润湿的导电膏被印刷在基底的接触垫上。 将半导体管芯设置在铝可润湿的导电膏上。 铝可湿性导电膏被回流以在衬底的接触焊盘上形成互连结构。 接触垫包括铝。 半导体管芯的接触焊盘设置在铝可润湿的导电膏上。 铝可润湿的导电膏被回流以在半导体管芯的接触焊盘和衬底的接触焊盘之间形成互连结构。 互连结构直接形成在基板和半导体管芯的接触焊盘上。 在回流铝可湿性导电膏之前，蚀刻半导体管芯的接触焊盘。 环氧预处理点，以保持半导体管芯和衬底之间的间隔。

公开(公告)号：US20140175639A1

公开(公告)日：2014-06-26

申请号：US14038339

申请日：2013-09-26

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HeeJo Chi

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81907 ,  H01L2224/8191 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material.

Abstract translation: 半导体器件具有设置在衬底上的半导体管芯。 将半导体管芯和衬底放置在追逐模具中。 在半导体管芯和衬底之上和之间沉积密封剂，同时将半导体管芯与追逐模具中的衬底结合。 通过施加力和升高的温度，使用热压将半导体管芯结合到衬底上。 在半导体管芯上方形成电连接结构，例如凸块，柱凸块或凸块。 焊剂材料沉积在互连结构上。 在基板的导电层上沉积焊膏或SOP。 焊剂材料和SOP在半导体管芯和衬底之间提供临时粘结。 互连结构与SOP结合。 或者，互连结构可以直接结合到衬底的导电层，具有或不具有助焊剂材料。

公开(公告)号：US09666500B2

公开(公告)日：2017-05-30

申请号：US14697352

申请日：2015-04-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/31 ,  H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

公开(公告)号：US09496195B2

公开(公告)日：2016-11-15

申请号：US13832809

申请日：2013-03-15

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Heinz-Peter Wirtz ,  Seung Wook Yoon ,  Pandi C. Marimuthu

IPC: H01L21/56 ,  H01L23/28 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/565 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

Abstract translation: 半导体器件具有包括多个半导体管芯的半导体晶片。 在半导体晶片上形成绝缘层。 通过LDA去除绝缘层的一部分以暴露半导体管芯的有效表面的一部分。 在半导体管芯的有源表面上的接触焊盘上形成第一导电层。 单个半导体晶片以分离半导体管芯。 半导体管芯设置在载体上，半导体管芯的有源表面与载体偏移。 在半导体管芯和载体上沉积密封剂以覆盖半导体管芯的一侧和有源表面的暴露部分。 在第一导电层上形成互连结构。 或者，MUF材料沉积在半导体管芯的一侧和有源表面的暴露部分上。

公开(公告)号：US20160163675A1

公开(公告)日：2016-06-09

申请号：US15012346

申请日：2016-02-01

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HunTeak Lee ,  HeeJo Chi

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

Abstract translation: 半导体器件具有设置在载体上的多个半导体管芯。 在半导体管芯上方形成诸如柱形凸块的电互连。 螺柱凸块被修剪成均匀的高度。 衬底包括在衬底上的凸块。 将半导体管芯的电气互连结合到衬底的凸块上，同时将半导体管芯设置在载体上。 在半导体管芯和衬底之间沉积底部填充材料。 或者，使用追逐模具在半导体管芯和衬底上沉积密封剂。 半导体管芯的凸起凸块与衬底的凸起的接合是使用回流焊或热压而进行的，同时半导体管芯是重新构成的晶片形式并且附着到载体上，以提供与衬底的倒装芯片型互连的高通量。

公开(公告)号：US20150380339A1

公开(公告)日：2015-12-31

申请号：US14316561

申请日：2014-06-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Xing Zhao ,  Duk Ju Na ,  Siew Joo Tan ,  Pandi C. Marimuthu

IPC: H01L23/48 ,  H01L21/306 ,  H01L25/065 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03602 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/13091 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01007 ,  H01L2924/01082

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.

Abstract translation: 半导体器件具有通过半导体晶片形成的半导体晶片和导电通孔。 去除半导体晶片的一部分，使得导电通孔的一部分延伸到半导体晶片之上。 在导电通孔和半导体晶片之上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 第一绝缘层包括无机材料，第二绝缘层包括有机材料。 通过化学机械抛光（CMP），第一和第二绝缘层的一部分被同时从导电通孔上除去。 或者，在导电通孔和半导体晶片之上形成包括有机材料的第一绝缘层。 通过CMP去除第一绝缘层的一部分。 导电层形成在导电通孔和第一绝缘层之上。 导电层基本上是平面的。

公开(公告)号：US20150228552A1

公开(公告)日：2015-08-13

申请号：US14697352

申请日：2015-04-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/528

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US20150091145A1

公开(公告)日：2015-04-02

申请号：US14566870

申请日：2014-12-11

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76829 ,  H01L21/4832 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06182 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.

Abstract translation: 半导体器件具有安装在载体上的半导体管芯。 封装剂沉积在载体和半导体管芯上。 载体被移除。 在密封剂和模具的第一表面上形成第一互连结构。 在密封剂和模具的第二表面上形成第二互连结构。 在第一互连结构之上形成第一保护层，并且在形成通孔之前在第二互连结构上形成第二保护层。 通过第二互连结构，密封剂和第一互连结构形成多个通孔。 在通孔中形成第一导电层以电连接第一互连结构和第二互连结构。 绝缘层形成在第一互连结构和第二互连结构之上，并且形成在通孔中。 分立半导体部件可以安装到第一互连结构。